|
251 | 251 | states = <1800000 0x0>,
|
252 | 252 | <3300000 0x1>;
|
253 | 253 | };
|
| 254 | + |
| 255 | + dp0_pwr_3v3: regulator-dp0-pwr { |
| 256 | + compatible = "regulator-fixed"; |
| 257 | + regulator-name = "dp0-pwr"; |
| 258 | + regulator-min-microvolt = <3300000>; |
| 259 | + regulator-max-microvolt = <3300000>; |
| 260 | + pinctrl-names = "default"; |
| 261 | + pinctrl-0 = <&dp_pwr_en_pins_default>; |
| 262 | + gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */ |
| 263 | + enable-active-high; |
| 264 | + }; |
| 265 | + |
| 266 | + dp0: connector-dp0 { |
| 267 | + compatible = "dp-connector"; |
| 268 | + label = "DP0"; |
| 269 | + type = "full-size"; |
| 270 | + dp-pwr-supply = <&dp0_pwr_3v3>; |
| 271 | + |
| 272 | + port { |
| 273 | + dp0_connector_in: endpoint { |
| 274 | + remote-endpoint = <&dp0_out>; |
| 275 | + }; |
| 276 | + }; |
| 277 | + }; |
| 278 | + |
| 279 | + connector-hdmi { |
| 280 | + compatible = "hdmi-connector"; |
| 281 | + label = "hdmi"; |
| 282 | + type = "a"; |
| 283 | + pinctrl-names = "default"; |
| 284 | + pinctrl-0 = <&hdmi_hpd_pins_default>; |
| 285 | + ddc-i2c-bus = <&mcu_i2c1>; |
| 286 | + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */ |
| 287 | + |
| 288 | + port { |
| 289 | + hdmi_connector_in: endpoint { |
| 290 | + remote-endpoint = <&tfp410_out>; |
| 291 | + }; |
| 292 | + }; |
| 293 | + }; |
| 294 | + |
| 295 | + bridge-dvi { |
| 296 | + compatible = "ti,tfp410"; |
| 297 | + pinctrl-names = "default"; |
| 298 | + pinctrl-0 = <&hdmi_pdn_pins_default>; |
| 299 | + powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */ |
| 300 | + ti,deskew = <0>; |
| 301 | + |
| 302 | + ports { |
| 303 | + #address-cells = <1>; |
| 304 | + #size-cells = <0>; |
| 305 | + |
| 306 | + port@0 { |
| 307 | + reg = <0>; |
| 308 | + |
| 309 | + tfp410_in: endpoint { |
| 310 | + remote-endpoint = <&dpi1_out0>; |
| 311 | + pclk-sample = <1>; |
| 312 | + }; |
| 313 | + }; |
| 314 | + |
| 315 | + port@1 { |
| 316 | + reg = <1>; |
| 317 | + |
| 318 | + tfp410_out: endpoint { |
| 319 | + remote-endpoint = <&hdmi_connector_in>; |
| 320 | + }; |
| 321 | + }; |
| 322 | + }; |
| 323 | + }; |
254 | 324 | };
|
255 | 325 |
|
256 | 326 | &main_pmx0 {
|
|
308 | 378 | J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
|
309 | 379 | >;
|
310 | 380 | };
|
| 381 | + |
| 382 | + dp0_pins_default: dp0-default-pins { |
| 383 | + pinctrl-single,pins = < |
| 384 | + J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ |
| 385 | + >; |
| 386 | + }; |
| 387 | + |
| 388 | + dp_pwr_en_pins_default: dp-pwr-en-default-pins { |
| 389 | + pinctrl-single,pins = < |
| 390 | + J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */ |
| 391 | + >; |
| 392 | + }; |
| 393 | + |
| 394 | + dss_vout0_pins_default: dss-vout0-default-pins { |
| 395 | + pinctrl-single,pins = < |
| 396 | + J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */ |
| 397 | + J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */ |
| 398 | + J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */ |
| 399 | + J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */ |
| 400 | + J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */ |
| 401 | + J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */ |
| 402 | + J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */ |
| 403 | + J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */ |
| 404 | + J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */ |
| 405 | + J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */ |
| 406 | + J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */ |
| 407 | + J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */ |
| 408 | + J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */ |
| 409 | + J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */ |
| 410 | + J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */ |
| 411 | + J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */ |
| 412 | + J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */ |
| 413 | + J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */ |
| 414 | + J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */ |
| 415 | + J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */ |
| 416 | + J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */ |
| 417 | + J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */ |
| 418 | + J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */ |
| 419 | + J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */ |
| 420 | + J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */ |
| 421 | + J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */ |
| 422 | + J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */ |
| 423 | + J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */ |
| 424 | + >; |
| 425 | + }; |
| 426 | + |
| 427 | + hdmi_hpd_pins_default: hdmi-hpd-default-pins { |
| 428 | + pinctrl-single,pins = < |
| 429 | + J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ |
| 430 | + >; |
| 431 | + }; |
311 | 432 | };
|
312 | 433 |
|
313 | 434 | &wkup_pmx2 {
|
|
382 | 503 | J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
|
383 | 504 | >;
|
384 | 505 | };
|
| 506 | + |
| 507 | + mcu_i2c1_pins_default: mcu-i2c1-default-pins { |
| 508 | + pinctrl-single,pins = < |
| 509 | + /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ |
| 510 | + J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) |
| 511 | + /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ |
| 512 | + J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) |
| 513 | + >; |
| 514 | + }; |
| 515 | + |
| 516 | + hdmi_pdn_pins_default: hdmi-pdn-default-pins { |
| 517 | + pinctrl-single,pins = < |
| 518 | + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ |
| 519 | + >; |
| 520 | + }; |
385 | 521 | };
|
386 | 522 |
|
387 | 523 | &wkup_pmx3 {
|
|
666 | 802 | memory-region = <&c71_3_dma_memory_region>,
|
667 | 803 | <&c71_3_memory_region>;
|
668 | 804 | };
|
| 805 | + |
| 806 | +&wkup_gpio_intr { |
| 807 | + status = "okay"; |
| 808 | +}; |
| 809 | + |
| 810 | +&mcu_i2c1 { |
| 811 | + status = "okay"; |
| 812 | + pinctrl-names = "default"; |
| 813 | + pinctrl-0 = <&mcu_i2c1_pins_default>; |
| 814 | + clock-frequency = <100000>; |
| 815 | +}; |
| 816 | + |
| 817 | +&serdes_refclk { |
| 818 | + status = "okay"; |
| 819 | + clock-frequency = <100000000>; |
| 820 | +}; |
| 821 | + |
| 822 | +&dss { |
| 823 | + status = "okay"; |
| 824 | + pinctrl-names = "default"; |
| 825 | + pinctrl-0 = <&dss_vout0_pins_default>; |
| 826 | + assigned-clocks = <&k3_clks 218 2>, |
| 827 | + <&k3_clks 218 5>, |
| 828 | + <&k3_clks 218 14>, |
| 829 | + <&k3_clks 218 18>; |
| 830 | + assigned-clock-parents = <&k3_clks 218 3>, |
| 831 | + <&k3_clks 218 7>, |
| 832 | + <&k3_clks 218 16>, |
| 833 | + <&k3_clks 218 22>; |
| 834 | +}; |
| 835 | + |
| 836 | +&serdes_wiz4 { |
| 837 | + status = "okay"; |
| 838 | +}; |
| 839 | + |
| 840 | +&serdes4 { |
| 841 | + status = "okay"; |
| 842 | + serdes4_dp_link: phy@0 { |
| 843 | + reg = <0>; |
| 844 | + cdns,num-lanes = <4>; |
| 845 | + #phy-cells = <0>; |
| 846 | + cdns,phy-type = <PHY_TYPE_DP>; |
| 847 | + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, |
| 848 | + <&serdes_wiz4 3>, <&serdes_wiz4 4>; |
| 849 | + }; |
| 850 | +}; |
| 851 | + |
| 852 | +&mhdp { |
| 853 | + status = "okay"; |
| 854 | + pinctrl-names = "default"; |
| 855 | + pinctrl-0 = <&dp0_pins_default>; |
| 856 | + phys = <&serdes4_dp_link>; |
| 857 | + phy-names = "dpphy"; |
| 858 | +}; |
| 859 | + |
| 860 | +&dss_ports { |
| 861 | + #address-cells = <1>; |
| 862 | + #size-cells = <0>; |
| 863 | + |
| 864 | + /* DP */ |
| 865 | + port@0 { |
| 866 | + reg = <0>; |
| 867 | + |
| 868 | + dpi0_out: endpoint { |
| 869 | + remote-endpoint = <&dp0_in>; |
| 870 | + }; |
| 871 | + }; |
| 872 | + |
| 873 | + /* HDMI */ |
| 874 | + port@1 { |
| 875 | + reg = <1>; |
| 876 | + |
| 877 | + dpi1_out0: endpoint { |
| 878 | + remote-endpoint = <&tfp410_in>; |
| 879 | + }; |
| 880 | + }; |
| 881 | +}; |
| 882 | + |
| 883 | +&dp0_ports { |
| 884 | + |
| 885 | + port@0 { |
| 886 | + reg = <0>; |
| 887 | + |
| 888 | + dp0_in: endpoint { |
| 889 | + remote-endpoint = <&dpi0_out>; |
| 890 | + }; |
| 891 | + }; |
| 892 | + |
| 893 | + port@4 { |
| 894 | + reg = <4>; |
| 895 | + |
| 896 | + dp0_out: endpoint { |
| 897 | + remote-endpoint = <&dp0_connector_in>; |
| 898 | + }; |
| 899 | + }; |
| 900 | +}; |
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