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Merge pull request The-OpenROAD-Project#3419 from The-OpenROAD-Project-staging/secure-retire-mergelib
synth: Rm `.lib` preprocess after tools improved
2 parents f3e24b1 + dbfe229 commit bb27eaa

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‎docs/user/FlowVariables.md‎

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Original file line numberDiff line numberDiff line change
@@ -126,7 +126,6 @@ configuration file.
126126
| <a name="DFF_LIB_FILES"></a>DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| |
127127
| <a name="DIE_AREA"></a>DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
128128
| <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| |
129-
| <a name="DONT_USE_LIBS"></a>DONT_USE_LIBS| Set liberty files as `dont_use`.| |
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| <a name="DPO_MAX_DISPLACEMENT"></a>DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1|
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| <a name="EARLY_SIZING_CAP_RATIO"></a>EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| |
132131
| <a name="ENABLE_DPO"></a>ENABLE_DPO| Enable detail placement with improve_placement feature.| 1|
@@ -470,7 +469,6 @@ configuration file.
470469
- [DESIGN_NICKNAME](#DESIGN_NICKNAME)
471470
- [DFF_LIB_FILES](#DFF_LIB_FILES)
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- [DONT_USE_CELLS](#DONT_USE_CELLS)
473-
- [DONT_USE_LIBS](#DONT_USE_LIBS)
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- [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT)
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- [ENABLE_DPO](#ENABLE_DPO)
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- [FASTROUTE_TCL](#FASTROUTE_TCL)

‎flow/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -179,19 +179,6 @@ build_macros: $(BLOCK_LEFS) $(BLOCK_TYP_LIBS)
179179
$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk)))
180180
$(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef))
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182-
# Pre-process libraries
183-
# ==============================================================================
184-
185-
# Create temporary Liberty files which have the proper dont_use properties set
186-
# For use with Yosys and ABC
187-
.SECONDEXPANSION:
188-
$(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
189-
@mkdir -p $(OBJECTS_DIR)/lib
190-
$(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@
191-
192-
$(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS)
193-
$(PYTHON_EXE) $(UTILS_DIR)/merge_lib.py $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
194-
195182
# Pre-process KLayout tech
196183
# ==============================================================================
197184
$(OBJECTS_DIR)/klayout_tech.lef: $(TECH_LEF)
@@ -272,11 +259,11 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
272259
yosys-dependencies: $(YOSYS_DEPENDENCIES)
273260

274261
.PHONY: do-yosys
275-
do-yosys: $(DONT_USE_SC_LIB)
262+
do-yosys: yosys-dependencies
276263
$(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log
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278265
.PHONY: do-yosys-canonicalize
279-
do-yosys-canonicalize: yosys-dependencies $(DONT_USE_SC_LIB)
266+
do-yosys-canonicalize: yosys-dependencies
280267
$(SCRIPTS_DIR)/synth.sh $(SCRIPTS_DIR)/synth_canonicalize.tcl $(LOG_DIR)/1_1_yosys_canonicalize.log
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282269
$(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil: $(YOSYS_DEPENDENCIES)
@@ -405,7 +392,7 @@ endef
405392

406393
$(eval $(call do-step,1_3_synth,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc,synth_odb))
407394

408-
$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(DONT_USE_SC_LIB) $(IO_CONSTRAINTS),floorplan))
395+
$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(LIB_FILES) $(IO_CONSTRAINTS),floorplan))
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410397
$(eval $(call do-copy,2_floorplan,2_1_floorplan.sdc,,.sdc))
411398

‎flow/designs/gf180/aes-hybrid/rules-base.json‎

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Original file line numberDiff line numberDiff line change
@@ -1,18 +1,18 @@
11
{
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"synth__design__instance__area__stdcell": {
3-
"value": 624425.81,
3+
"value": 493531.52,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
99
},
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"placeopt__design__instance__area": {
11-
"value": 798562,
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"value": 657615,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
15-
"value": 22568,
15+
"value": 22088,
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"compare": "<="
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},
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"detailedplace__design__violations": {
@@ -28,11 +28,11 @@
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"compare": "<="
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},
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"globalroute__antenna_diodes_count": {
31-
"value": 3,
31+
"value": 2,
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"compare": "<="
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},
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"detailedroute__route__wirelength": {
35-
"value": 1623163,
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"value": 1503800,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -44,15 +44,15 @@
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"compare": "<="
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},
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"detailedroute__antenna_diodes_count": {
47-
"value": 5,
47+
"value": 9,
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"compare": "<="
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},
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"finish__timing__setup__ws": {
51-
"value": -1.16,
51+
"value": -1.35,
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"compare": ">="
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},
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"finish__design__instance__area": {
55-
"value": 803898,
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"value": 779709,
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"compare": "<="
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},
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"finish__timing__drv__setup_violation_count": {

‎flow/platforms/asap7/config.mk‎

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@@ -201,11 +201,6 @@ export DB_FILES += $(realpath $($(CORNER)_DB_FILES))
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export TEMPERATURE = $($(CORNER)_TEMPERATURE)
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export VOLTAGE = $($(CORNER)_VOLTAGE)
203203

204-
# FIXME Need merged.lib for now, but ideally it shouldn't be necessary:
205-
#
206-
# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/2139
207-
export DONT_USE_SC_LIB = $(OBJECTS_DIR)/lib/merged.lib
208-
209204
# ---------------------------------------------------------
210205
# IR Drop
211206
# ---------------------------------------------------------

‎flow/platforms/asap7/openRoad/post_mergeLib.py‎

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This file was deleted.

‎flow/scripts/synth.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -107,17 +107,12 @@ if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } {
107107
techmap -map $::env(LATCH_MAP_FILE)
108108
}
109109

110-
set dfflibmap_args ""
111-
foreach cell $::env(DONT_USE_CELLS) {
112-
lappend dfflibmap_args -dont_use $cell
113-
}
114-
115110
# Technology mapping of flip-flops
116111
# dfflibmap only supports one liberty file
117112
if { [env_var_exists_and_non_empty DFF_LIB_FILE] } {
118-
dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
113+
dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$lib_dont_use_args
119114
} else {
120-
dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
115+
dfflibmap {*}$lib_args {*}$lib_dont_use_args
121116
}
122117
opt
123118

@@ -152,7 +147,7 @@ insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS)
152147
# Reports
153148
tee -o $::env(REPORTS_DIR)/synth_check.txt check
154149

155-
tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
150+
tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$lib_args
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157152
# check the design is composed exclusively of target cells, and
158153
# check for other problems

‎flow/scripts/synth_preamble.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -94,20 +94,25 @@ if { $::env(ABC_AREA) } {
9494
set abc_script $::env(SCRIPTS_DIR)/abc_speed.script
9595
}
9696

97-
# Technology mapping for cells
98-
# ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't
99-
set abc_args [list -script $abc_script \
100-
-liberty $::env(DONT_USE_SC_LIB) \
101-
-constr $::env(OBJECTS_DIR)/abc.constr]
97+
# Create argument list for stat
98+
set lib_args ""
99+
foreach lib $::env(LIB_FILES) {
100+
append lib_args "-liberty $lib "
101+
}
102102

103103
# Exclude dont_use cells. This includes macros that are specified via
104104
# LIB_FILES and ADDITIONAL_LIBS that are included in LIB_FILES.
105+
set lib_dont_use_args ""
105106
if { [env_var_exists_and_non_empty DONT_USE_CELLS] } {
106107
foreach cell $::env(DONT_USE_CELLS) {
107-
lappend abc_args -dont_use $cell
108+
lappend lib_dont_use_args -dont_use $cell
108109
}
109110
}
110111

112+
# Technology mapping for cells
113+
set abc_args [list -script $abc_script \
114+
{*}$lib_args {*}$lib_dont_use_args -constr $::env(OBJECTS_DIR)/abc.constr]
115+
111116
if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } {
112117
puts "Extracting clock period from SDC file: $::env(SDC_FILE_CLOCK_PERIOD)"
113118
set fp [open $::env(SDC_FILE_CLOCK_PERIOD) r]
@@ -119,12 +124,6 @@ if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } {
119124
close $fp
120125
}
121126

122-
# Create argument list for stat
123-
set stat_libs ""
124-
foreach lib $::env(DONT_USE_LIBS) {
125-
append stat_libs "-liberty $lib "
126-
}
127-
128127
set constr [open $::env(OBJECTS_DIR)/abc.constr w]
129128
puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)"
130129
puts $constr "set_load $::env(ABC_LOAD_IN_FF)"

‎flow/scripts/synth_stdcells.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
# Read standard cells and macros as blackbox inputs
2-
# These libs have their dont_use properties set accordingly
3-
read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(DONT_USE_LIBS)
2+
read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(LIB_FILES)
43
read_liberty -overwrite -setattr liberty_cell \
5-
-unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(DONT_USE_LIBS)
4+
-unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(LIB_FILES)

‎flow/scripts/variables.mk‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -135,9 +135,6 @@ WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_m
135135
export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS)
136136
export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS)
137137

138-
export DONT_USE_LIBS = $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES))))
139-
export DONT_USE_SC_LIB ?= $(firstword $(DONT_USE_LIBS))
140-
141138
# Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS
142139
STREAM_SYSTEM ?= GDS
143140
ifneq ($(findstring GDS,$(shell echo $(STREAM_SYSTEM) | tr '[:lower:]' '[:upper:]')),)
@@ -166,7 +163,7 @@ export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH)
166163
export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl
167164
export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt
168165

169-
export YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
166+
export YOSYS_DEPENDENCIES=$(LIB_FILES) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
170167

171168
# Ubuntu 22.04 ships with older than 0.28.11, so support older versions
172169
# for a while still.

‎flow/scripts/variables.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -728,9 +728,6 @@ CDL_FILES:
728728
DFF_LIB_FILES:
729729
description: |
730730
Technology mapping liberty files for flip-flops.
731-
DONT_USE_LIBS:
732-
description: |
733-
Set liberty files as `dont_use`.
734731
SYNTH_KEEP_MODULES:
735732
description: |
736733
Mark modules to keep from getting removed in flattening.

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