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1 parent 30c606c commit c421ebdCopy full SHA for c421ebd
examples/snakepu/design.txt
@@ -16,7 +16,7 @@ snakePU MAIN REGISTERS:
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IR - Instruction register
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-- data
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- AR - Argument register - second byte of opcode (32bit)
+ AR - Argument register - second byte of opcode (64bit)
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INSTRUCTION PHASES:
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1. Fetch opcode -> IR, AR
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