Merge branch 'zephyrproject-rtos:main' into main

Author: kartben

.github/workflows/compliance.yml

@@ -66,9 +66,10 @@ jobs:
         node-version: "lts/*"
         cache: npm
         check-latest: true
+        cache-dependency-path: ./scripts/ci/package-lock.json
 
     - name: Install Node dependencies
-      run: npm ci
+      run: npm --prefix ./scripts/ci ci
 
     - name: Run Compliance Tests
       continue-on-error: true

.ruff-excludes.toml

@@ -1088,17 +1088,6 @@
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
 ]
-"./tests/drivers/can/host/pytest/can_shell.py" = [
-    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
-    "SIM401",   # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get
-    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
-    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
-    "UP045",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation-optional
-]
-"./tests/drivers/can/host/pytest/test_can.py" = [
-    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
-    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
-]
 "./tests/kernel/timer/timer_behavior/pytest/saleae_logic2.py" = [
     "B905",     # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
@@ -1481,9 +1470,6 @@ exclude = [
     "./tests/boot/with_mcumgr/pytest/test_downgrade_prevention.py",
     "./tests/boot/with_mcumgr/pytest/test_upgrade.py",
     "./tests/boot/with_mcumgr/pytest/west_sign_wrapper.py",
-    "./tests/drivers/can/host/pytest/can_shell.py",
-    "./tests/drivers/can/host/pytest/conftest.py",
-    "./tests/drivers/can/host/pytest/test_can.py",
     "./tests/kernel/timer/timer_behavior/pytest/saleae_logic2.py",
     "./tests/kernel/timer/timer_behavior/pytest/test_timer.py",
     "./tests/lib/devicetree/memory_region_flags/pytest/test_memory_region_flags.py",

CMakeLists.txt

@@ -737,6 +737,10 @@ zephyr_get(KERNEL_VERSION_CUSTOMIZATION SYSBUILD LOCAL)
 set_property(TARGET version_h PROPERTY KERNEL_VERSION_CUSTOMIZATION ${KERNEL_VERSION_CUSTOMIZATION})
 
 if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION)
+  # A generator expression is used to allow applications to add their own dependencies for the
+  # file version, this might typically be the git index file if the application is in a git
+  # repository. To add a dependency to the application version file, this can be used:
+  # set_property(TARGET app_version_h PROPERTY APP_VERSION_DEPENDS <FILE>)
   add_custom_command(
     OUTPUT ${PROJECT_BINARY_DIR}/include/generated/zephyr/app_version.h
     COMMAND ${CMAKE_COMMAND} -DZEPHYR_BASE=${ZEPHYR_BASE}
@@ -747,6 +751,7 @@ if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION)
       ${build_version_argument}
       -P ${ZEPHYR_BASE}/cmake/gen_version_h.cmake
     DEPENDS ${APPLICATION_SOURCE_DIR}/VERSION ${git_dependency}
+      $<TARGET_PROPERTY:app_version_h,APP_VERSION_DEPENDS>
     COMMAND_EXPAND_LISTS
   )
   add_custom_target(

VERSION

@@ -2,4 +2,4 @@ VERSION_MAJOR = 4
 VERSION_MINOR = 3
 PATCHLEVEL = 0
 VERSION_TWEAK = 0
-EXTRAVERSION = rc1
+EXTRAVERSION = rc2

arch/arm64/core/Kconfig

@@ -9,7 +9,7 @@ config CPU_CORTEX_A
 	select HAS_FLASH_LOAD_OFFSET
 	select SCHED_IPI_SUPPORTED if SMP
 	select CPU_HAS_FPU
-	select ARCH_HAS_SINGLE_THREAD_SUPPORT
+	select ARCH_HAS_SINGLE_THREAD_SUPPORT if !SMP
 	select CPU_HAS_DCACHE
 	select CPU_HAS_ICACHE
 	imply FPU

arch/xtensa/core/irq_manage.c

@@ -122,6 +122,7 @@ int xtensa_irq_is_enabled(unsigned int irq)
 		break;
 #endif
 	default:
+		ie = 0;
 		break;
 	}
 #else

boards/ambiq/apollo2_evb/doc/index.rst

@@ -7,7 +7,7 @@ Hardware
 
 The Ambiq Apollo2 SoC provides the following hardware features:
 
-- ARM® Cortex® M4F core with a Floating Point Unit
+- ARM® Cortex®-M4F core with a Floating Point Unit
 - Up to 48 MHz operating frequency
 - 16 kB 2-way Associative Cache
 - Up to 1 MB of flash memory for code/data

boards/ambiq/apollo3_evb/doc/index.rst

@@ -6,7 +6,7 @@ Hardware
 ********
 
 - Apollo3 Blue SoC with up to 96 MHz operating frequency
-- ARM® Cortex® M4F core
+- ARM® Cortex®-M4F core
 - 16 kB 2-way Associative/Direct-Mapped Cache per core
 - Up to 1 MB of flash memory for code/data
 - Up to 384 KB of low leakage / low power RAM for code/data

boards/ambiq/apollo3p_evb/doc/index.rst

@@ -6,7 +6,7 @@ Hardware
 ********
 
 - Apollo3 Blue Plus SoC with up to 96 MHz operating frequency
-- ARM® Cortex® M4F core
+- ARM® Cortex®-M4F core
 - 16 kB 2-way Associative/Direct-Mapped Cache per core
 - Up to 2 MB of flash memory for code/data
 - Up to 768 KB of low leakage / low power RAM for code/data

boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst

@@ -6,7 +6,7 @@ Hardware
 ********
 
 - Apollo4 Blue Plus SoC with upto 192 MHz operating frequency
-- ARM® Cortex® M4F core
+- ARM® Cortex®-M4F core
 - 64 kB 2-way Associative/Direct-Mapped Cache per core
 - Up to 2 MB of non-volatile memory (NVM) for code/data
 - Up to 2.75 MB of low leakage / low power RAM for code/data