riscv: irq: Set selective hardware vectoring

The mechanism for hardware vectoring has changed in the clic spec
(https://github.com/riscv/riscv-fast-interrupt) in 2019. Before
vectoring was enabled via `mode` bits in `mtvec`. Support for this was
added in fc480c9.

With more current clic implementations, this does not work anymore.
Changing the `mode` bits is reserved. Vectoring can be enabled
individually in the `shv` bit of `clicintattr[i]`.

Since the old mechanism is still used, I added a new Kconfig for it.

If this Kconfig is not set, we use the `shv` bit for harware vectoring.

Signed-off-by: Greter Raffael <[email protected]>

Author: raffi-g

drivers/interrupt_controller/Kconfig.clic

@@ -8,3 +8,10 @@ config NUCLEI_ECLIC
 	select MULTI_LEVEL_INTERRUPTS
 	help
 	  Interrupt controller for Nuclei SoC core.
+
+config LEGACY_CLIC
+	bool "Use the legacy clic specification"
+	depends on RISCV_HAS_CLIC
+	help
+	  Enables legacy clic, where smclicshv extension is not supported and
+	  hardware vectoring is set via mode bits of mtvec.

drivers/interrupt_controller/intc_nuclei_eclic.c

@@ -156,8 +156,19 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
 
 	ECLIC_CTRL[irq].INTCTRL = intctrl;
 
-	ECLIC_CTRL[irq].INTATTR.b.shv = 0;
-	ECLIC_CTRL[irq].INTATTR.b.trg = (uint8_t)(flags & CLIC_INTATTR_TRIG_Msk);
+	union CLICINTATTR intattr = {.w = 0};
+#if defined(CONFIG_RISCV_VECTORED_MODE) && !defined(CONFIG_LEGACY_CLIC)
+	/*
+	 * Set Selective Hardware Vectoring.
+	 * Legacy SiFive does not implement smclicshv extension and vectoring is
+	 * enabled in the mode bits of mtvec.
+	 */
+	intattr.b.shv = 1;
+#else
+	intattr.b.shv = 0;
+#endif
+	intattr.b.trg = (uint8_t)(flags & CLIC_INTATTR_TRIG_Msk);
+	ECLIC_CTRL[irq].INTATTR = intattr;
 }
 
 static int nuclei_eclic_init(const struct device *dev)