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Joel FernandesDanilo Krummrich
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Documentation: gpu: nova-core: Document vbios layout
Add detailed explanation and block diagrams of the layout of the vBIOS on Nvidia GPUs. This is important to understand how nova-core boots an Nvidia GPU. [ Applied Timur Tabi's feedback on providing link to BIT documentation. ] Signed-off-by: Joel Fernandes <[email protected]> Signed-off-by: Alexandre Courbot <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Danilo Krummrich <[email protected]>
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‎Documentation/gpu/nova/core/vbios.rst

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.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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==========
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VBIOS
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==========
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This document describes the layout of the VBIOS image which is a series of concatenated
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images in the ROM of the GPU. The VBIOS is mirrored onto the BAR 0 space and is read
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by both Boot ROM firmware (also known as IFR or init-from-rom firmware) on the GPU to
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bootstrap various microcontrollers (PMU, SEC, GSP) with critical initialization before
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the driver loads, as well as by the nova-core driver in the kernel to boot the GSP.
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The format of the images in the ROM follow the "BIOS Specification" part of the
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PCI specification, with Nvidia-specific extensions. The ROM images of type FwSec
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are the ones that contain Falcon ucode and what we are mainly looking for.
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As an example, the following are the different image types that can be found in the
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VBIOS of an Ampere GA102 GPU which is supported by the nova-core driver.
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- PciAt Image (Type 0x00) - This is the standard PCI BIOS image, whose name
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likely comes from the "IBM PC/AT" architecture.
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- EFI Image (Type 0x03) - This is the EFI BIOS image. It contains the UEFI GOP
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driver that is used to display UEFI graphics output.
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- First FwSec Image (Type 0xE0) - The first FwSec image (Secure Firmware)
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- Second FwSec Image (Type 0xE0) - The second FwSec image (Secure Firmware)
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contains various microcodes (also known as an applications) that do a range
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of different functions. The FWSEC ucode is run in heavy-secure mode and
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typically runs directly on the GSP (it could be running on a different
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designated processor in future generations but as of Ampere, it is the GSP).
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This firmware then loads other firmware ucodes onto the PMU and SEC2
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microcontrollers for gfw initialization after GPU reset and before the driver
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loads (see devinit.rst). The DEVINIT ucode is itself another ucode that is
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stored in this ROM partition.
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Once located, the Falcon ucodes have "Application Interfaces" in their data
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memory (DMEM). For FWSEC, the application interface we use for FWSEC is the
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"DMEM mapper" interface which is configured to run the "FRTS" command. This
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command carves out the WPR2 (Write-Protected Region) in VRAM. It then places
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important power-management data, called 'FRTS', into this region. The WPR2
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region is only accessible to heavy-secure ucode.
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.. note::
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It is not clear why FwSec has 2 different partitions in the ROM, but they both
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are of type 0xE0 and can be identified as such. This could be subject to change
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in future generations.
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VBIOS ROM Layout
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----------------
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The VBIOS layout is roughly a series of concatenated images laid out as follows::
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+----------------------------------------------------------------------------+
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| VBIOS (Starting at ROM_OFFSET: 0x300000) |
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+----------------------------------------------------------------------------+
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| +-----------------------------------------------+ |
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| | PciAt Image (Type 0x00) | |
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| +-----------------------------------------------+ |
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| | +-------------------+ | |
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| | | ROM Header | | |
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| | | (Signature 0xAA55)| | |
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| | +-------------------+ | |
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| | | rom header's pci_data_struct_offset | |
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| | | points to the PCIR structure | |
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| | V | |
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| | +-------------------+ | |
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| | | PCIR Structure | | |
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| | | (Signature "PCIR")| | |
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| | | last_image: 0x80 | | |
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| | | image_len: size | | |
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| | | in 512-byte units | | |
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| | +-------------------+ | |
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| | | | |
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| | | NPDE immediately follows PCIR | |
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| | V | |
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| | +-------------------+ | |
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| | | NPDE Structure | | |
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| | | (Signature "NPDE")| | |
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| | | last_image: 0x00 | | |
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| | +-------------------+ | |
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| | | |
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| | +-------------------+ | |
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| | | BIT Header | (Signature scanning | |
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| | | (Signature "BIT") | provides the location | |
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| | +-------------------+ of the BIT table) | |
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| | | header is | |
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| | | followed by a table of tokens | |
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| | V one of which is for falcon data. | |
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| | +-------------------+ | |
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| | | BIT Tokens | | |
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| | | ______________ | | |
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| | | | Falcon Data | | | |
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| | | | Token (0x70)|---+------------>------------+--+ |
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| | | +-------------+ | falcon_data_ptr() | | |
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| | +-------------------+ | V |
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| +-----------------------------------------------+ | |
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| (no gap between images) | |
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| +-----------------------------------------------+ | |
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| | EFI Image (Type 0x03) | | |
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| +-----------------------------------------------+ | |
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| | Contains the UEFI GOP driver (Graphics Output)| | |
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| | +-------------------+ | | |
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| | | ROM Header | | | |
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| | +-------------------+ | | |
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| | | PCIR Structure | | | |
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| | +-------------------+ | | |
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| | | NPDE Structure | | | |
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| | +-------------------+ | | |
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| | | Image data | | | |
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| | +-------------------+ | | |
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| +-----------------------------------------------+ | |
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| (no gap between images) | |
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| +-----------------------------------------------+ | |
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| | First FwSec Image (Type 0xE0) | | |
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| +-----------------------------------------------+ | |
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| | +-------------------+ | | |
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| | | ROM Header | | | |
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| | +-------------------+ | | |
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| | | PCIR Structure | | | |
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| | +-------------------+ | | |
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| | | NPDE Structure | | | |
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| | +-------------------+ | | |
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| | | Image data | | | |
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| | +-------------------+ | | |
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| +-----------------------------------------------+ | |
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| (no gap between images) | |
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| +-----------------------------------------------+ | |
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| | Second FwSec Image (Type 0xE0) | | |
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| +-----------------------------------------------+ | |
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| | +-------------------+ | | |
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| | | ROM Header | | | |
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| | +-------------------+ | | |
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| | | PCIR Structure | | | |
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| | +-------------------+ | | |
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| | | NPDE Structure | | | |
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| | +-------------------+ | | |
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| | | | |
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| | +-------------------+ | | |
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| | | PMU Lookup Table | <- falcon_data_offset <----+ |
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| | | +-------------+ | pmu_lookup_table | |
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| | | | Entry 0x85 | | | |
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| | | | FWSEC_PROD | | | |
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| | | +-------------+ | | |
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| | +-------------------+ | |
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| | | | |
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| | | points to | |
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| | V | |
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| | +-------------------+ | |
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| | | FalconUCodeDescV3 | <- falcon_ucode_offset | |
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| | | (FWSEC Firmware) | fwsec_header() | |
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| | +-------------------+ | |
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| | | immediately followed by... | |
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| | V | |
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| | +----------------------------+ | |
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| | | Signatures + FWSEC Ucode | | |
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| | | fwsec_sigs(), fwsec_ucode()| | |
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| | +----------------------------+ | |
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| +-----------------------------------------------+ |
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| |
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+----------------------------------------------------------------------------+
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.. note::
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This diagram is created based on an GA-102 Ampere GPU as an example and could
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vary for future or other GPUs.
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.. note::
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For more explanations of acronyms, see the detailed descriptions in `vbios.rs`.
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Falcon data Lookup
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------------------
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A key part of the VBIOS extraction code (vbios.rs) is to find the location of the
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Falcon data in the VBIOS which contains the PMU lookup table. This lookup table is
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used to find the required Falcon ucode based on an application ID.
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The location of the PMU lookup table is found by scanning the BIT (`BIOS Information Table`_)
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tokens for a token with the id `BIT_TOKEN_ID_FALCON_DATA` (0x70) which indicates the
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offset of the same from the start of the VBIOS image. Unfortunately, the offset
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does not account for the EFI image located between the PciAt and FwSec images.
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The `vbios.rs` code compensates for this with appropriate arithmetic.
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.. _`BIOS Information Table`: https://download.nvidia.com/open-gpu-doc/BIOS-Information-Table/1/BIOS-Information-Table.html

‎Documentation/gpu/nova/index.rst

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core/guidelines
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core/todo
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core/vbios

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