Skip to content

Commit d17e3f8

Browse files
Marc Zyngierbjorn-helgaas
authored andcommitted
PCI: xgene-msi: Make per-CPU interrupt setup robust
The way the per-CPU interrupts are dealt with in the XGene MSI driver isn't great: - the affinity is set after the interrupt is enabled - nothing prevents userspace from moving the interrupt around - the affinity setting code pointlessly allocates memory - the driver checks for conditions that cannot possibly happen Address all of this in one go, resulting in slightly simpler setup code. Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/r/[email protected]
1 parent fddf72e commit d17e3f8

File tree

1 file changed

+6
-23
lines changed

1 file changed

+6
-23
lines changed

drivers/pci/controller/pci-xgene-msi.c

Lines changed: 6 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -355,40 +355,26 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu)
355355
{
356356
struct xgene_msi *msi = &xgene_msi_ctrl;
357357
struct xgene_msi_group *msi_group;
358-
cpumask_var_t mask;
359358
int i;
360359
int err;
361360

362361
for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
363362
msi_group = &msi->msi_groups[i];
364-
if (!msi_group->gic_irq)
365-
continue;
366-
367-
irq_set_chained_handler_and_data(msi_group->gic_irq,
368-
xgene_msi_isr, msi_group);
369363

370364
/*
371365
* Statically allocate MSI GIC IRQs to each CPU core.
372366
* With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated
373367
* to each core.
374368
*/
375-
if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
376-
cpumask_clear(mask);
377-
cpumask_set_cpu(cpu, mask);
378-
err = irq_set_affinity(msi_group->gic_irq, mask);
379-
if (err)
380-
pr_err("failed to set affinity for GIC IRQ");
381-
free_cpumask_var(mask);
382-
} else {
383-
pr_err("failed to alloc CPU mask for affinity\n");
384-
err = -EINVAL;
385-
}
386-
369+
irq_set_status_flags(msi_group->gic_irq, IRQ_NO_BALANCING);
370+
err = irq_set_affinity(msi_group->gic_irq, cpumask_of(cpu));
387371
if (err) {
388-
irq_set_chained_handler_and_data(msi_group->gic_irq,
389-
NULL, NULL);
372+
pr_err("failed to set affinity for GIC IRQ");
390373
return err;
391374
}
375+
376+
irq_set_chained_handler_and_data(msi_group->gic_irq,
377+
xgene_msi_isr, msi_group);
392378
}
393379

394380
return 0;
@@ -402,9 +388,6 @@ static int xgene_msi_hwirq_free(unsigned int cpu)
402388

403389
for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
404390
msi_group = &msi->msi_groups[i];
405-
if (!msi_group->gic_irq)
406-
continue;
407-
408391
irq_set_chained_handler_and_data(msi_group->gic_irq, NULL,
409392
NULL);
410393
}

0 commit comments

Comments
 (0)