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klensy
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working tests from llvm#93673 
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‎llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ define void @broadcast() #0{
3131
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector <vscale x 8 x i1> undef, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
3232
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector <vscale x 4 x i1> undef, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
3333
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector <vscale x 2 x i1> undef, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
34-
; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void
34+
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
3535

3636
%zero = shufflevector <vscale x 16 x i8> undef, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
3737
%1 = shufflevector <vscale x 32 x i8> undef, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer

‎llvm/test/Assembler/bfloat.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,25 +37,25 @@ define float @check_bfloat_convert() {
3737
ret float %tmp
3838
}
3939

40-
; ASSEM-DISASS-LABEL @snan_bfloat
40+
; ASSEM-DISASS-LABEL: @snan_bfloat
4141
define bfloat @snan_bfloat() {
4242
; ASSEM-DISASS: ret bfloat 0xR7F81
4343
ret bfloat 0xR7F81
4444
}
4545

46-
; ASSEM-DISASS-LABEL @qnan_bfloat
46+
; ASSEM-DISASS-LABEL: @qnan_bfloat
4747
define bfloat @qnan_bfloat() {
4848
; ASSEM-DISASS: ret bfloat 0xR7FC0
4949
ret bfloat 0xR7FC0
5050
}
5151

52-
; ASSEM-DISASS-LABEL @pos_inf_bfloat
52+
; ASSEM-DISASS-LABEL: @pos_inf_bfloat
5353
define bfloat @pos_inf_bfloat() {
5454
; ASSEM-DISASS: ret bfloat 0xR7F80
5555
ret bfloat 0xR7F80
5656
}
5757

58-
; ASSEM-DISASS-LABEL @neg_inf_bfloat
58+
; ASSEM-DISASS-LABEL: @neg_inf_bfloat
5959
define bfloat @neg_inf_bfloat() {
6060
; ASSEM-DISASS: ret bfloat 0xRFF80
6161
ret bfloat 0xRFF80

‎llvm/test/CodeGen/AArch64/arm64_32-atomics.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,70 +2,70 @@
22
; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
33

44
define i8 @test_load_8(ptr %addr) {
5-
; CHECK-LABAL: test_load_8:
5+
; CHECK-LABEL: test_load_8:
66
; CHECK: ldarb w0, [x0]
77
%val = load atomic i8, ptr %addr seq_cst, align 1
88
ret i8 %val
99
}
1010

1111
define i16 @test_load_16(ptr %addr) {
12-
; CHECK-LABAL: test_load_16:
12+
; CHECK-LABEL: test_load_16:
1313
; CHECK: ldarh w0, [x0]
1414
%val = load atomic i16, ptr %addr acquire, align 2
1515
ret i16 %val
1616
}
1717

1818
define i32 @test_load_32(ptr %addr) {
19-
; CHECK-LABAL: test_load_32:
19+
; CHECK-LABEL: test_load_32:
2020
; CHECK: ldar w0, [x0]
2121
%val = load atomic i32, ptr %addr seq_cst, align 4
2222
ret i32 %val
2323
}
2424

2525
define i64 @test_load_64(ptr %addr) {
26-
; CHECK-LABAL: test_load_64:
26+
; CHECK-LABEL: test_load_64:
2727
; CHECK: ldar x0, [x0]
2828
%val = load atomic i64, ptr %addr seq_cst, align 8
2929
ret i64 %val
3030
}
3131

3232
define ptr @test_load_ptr(ptr %addr) {
33-
; CHECK-LABAL: test_load_ptr:
33+
; CHECK-LABEL: test_load_ptr:
3434
; CHECK: ldar w0, [x0]
3535
%val = load atomic ptr, ptr %addr seq_cst, align 8
3636
ret ptr %val
3737
}
3838

3939
define void @test_store_8(ptr %addr) {
40-
; CHECK-LABAL: test_store_8:
40+
; CHECK-LABEL: test_store_8:
4141
; CHECK: stlrb wzr, [x0]
4242
store atomic i8 0, ptr %addr seq_cst, align 1
4343
ret void
4444
}
4545

4646
define void @test_store_16(ptr %addr) {
47-
; CHECK-LABAL: test_store_16:
47+
; CHECK-LABEL: test_store_16:
4848
; CHECK: stlrh wzr, [x0]
4949
store atomic i16 0, ptr %addr seq_cst, align 2
5050
ret void
5151
}
5252

5353
define void @test_store_32(ptr %addr) {
54-
; CHECK-LABAL: test_store_32:
54+
; CHECK-LABEL: test_store_32:
5555
; CHECK: stlr wzr, [x0]
5656
store atomic i32 0, ptr %addr seq_cst, align 4
5757
ret void
5858
}
5959

6060
define void @test_store_64(ptr %addr) {
61-
; CHECK-LABAL: test_store_64:
61+
; CHECK-LABEL: test_store_64:
6262
; CHECK: stlr xzr, [x0]
6363
store atomic i64 0, ptr %addr seq_cst, align 8
6464
ret void
6565
}
6666

6767
define void @test_store_ptr(ptr %addr) {
68-
; CHECK-LABAL: test_store_ptr:
68+
; CHECK-LABEL: test_store_ptr:
6969
; CHECK: stlr wzr, [x0]
7070
store atomic ptr null, ptr %addr seq_cst, align 8
7171
ret void

‎llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s
22

33
define void @no_op() nounwind {
4-
; CHECK-LABEL .def $ientry_thunk$cdecl$v$v;
4+
; CHECK-LABEL: .def $ientry_thunk$cdecl$v$v;
55
; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v
66
; CHECK: // %bb.0:
77
; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill

‎llvm/test/CodeGen/AArch64/fpimm.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ define void @check_double() {
3838
; 64-bit ORR followed by MOVK.
3939
; CHECK-DAG: mov [[XFP0:x[0-9]+]], #1082331758844
4040
; CHECK-DAG: movk [[XFP0]], #64764, lsl #16
41-
; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]]
41+
; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]]
4242
%newval3 = fadd double %val, 0xFCFCFC00FC
4343
store volatile double %newval3, ptr @varf64
4444

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" {
2828
}
2929

3030
define void @b() "sign-return-address"="non-leaf" {
31-
; CHECK-LABE: b: // @b
31+
; CHECK-LABEL: b: // @b
3232
; V8A-NOT: hint #25
3333
; V83A-NOT: paciasp
3434
; CHECK-NOT: .cfi_negate_ra_state

‎llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@ entry:
192192
; CHECK: .Lfunc_end
193193
}
194194

195-
; HARDEN-label: __llvm_slsblr_thunk_x0:
195+
; HARDEN-LABEL: __llvm_slsblr_thunk_x0:
196196
; HARDEN: mov x16, x0
197197
; HARDEN: br x16
198198
; ISBDSB-NEXT: dsb sy
@@ -208,7 +208,7 @@ entry:
208208
; HARDEN-COMDAT-OFF-NOT: .hidden __llvm_slsblr_thunk_x19
209209
; HARDEN-COMDAT-OFF-NOT: .weak __llvm_slsblr_thunk_x19
210210
; HARDEN-COMDAT-OFF: .type __llvm_slsblr_thunk_x19,@function
211-
; HARDEN-label: __llvm_slsblr_thunk_x19:
211+
; HARDEN-LABEL: __llvm_slsblr_thunk_x19:
212212
; HARDEN: mov x16, x19
213213
; HARDEN: br x16
214214
; ISBDSB-NEXT: dsb sy

‎llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212

1313
# This test also checks that pairwise store STP is generated.
1414

15-
# CHECK-LABLE: test
15+
# CHECK-LABEL: test
1616
# CHECK: bb.0:
1717
# CHECK-NEXT: liveins: $x0, $x17, $x18
1818
# CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)

‎llvm/test/CodeGen/ARM/dsp-loop-indexing.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
; CHECK-DEFAULT: ldr{{.*}}, #4]
2323
; CHECK-DEFAULT: str{{.*}}, #4]
2424
; CHECK-DEFAULT: ldr{{.*}}, #8]!
25-
; CHECK-DEAFULT: ldr{{.*}}, #8]!
25+
; CHECK-DEFAULT: ldr{{.*}}, #8]!
2626
; CHECK-DEFAULT: str{{.*}}, #8]!
2727

2828
; CHECK-COMPLEX: ldr{{.*}}, #8]!

‎llvm/test/CodeGen/ARM/shifter_operand.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,6 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
121121
; CHECK-THUMB-NEXT: orrs r0, r1
122122
; CHECK-THUMB-NEXT: bx lr
123123
entry:
124-
; CHECk-THUMB: orrs r0, r1
125124
%mul = mul i32 %y, 63767
126125
%or = or i32 %mul, %x
127126
ret i32 %or

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