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lenarylenary
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Move Comments from Header
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 57 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -38,14 +38,6 @@ def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
3838
def SDT_RISCVBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
3939
SDTCisVT<2, OtherVT>,
4040
SDTCisVT<3, OtherVT>]>;
41-
def SDT_RISCVReadCSR : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>;
42-
def SDT_RISCVWriteCSR : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
43-
def SDT_RISCVSwapCSR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
44-
SDTCisInt<2>]>;
45-
def SDT_RISCVReadCounterWide : SDTypeProfile<2, 2, [SDTCisVT<0, i32>,
46-
SDTCisVT<1, i32>,
47-
SDTCisInt<2>,
48-
SDTCisInt<3>]>;
4941
def SDT_RISCVIntUnaryOpW : SDTypeProfile<1, 1, [
5042
SDTCisSameAs<0, 1>, SDTCisVT<0, i64>
5143
]>;
@@ -62,13 +54,21 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
6254
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
6355
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
6456

65-
// Target-dependent nodes.
6657
def riscv_call : RVSDNode<"CALL", SDT_RISCVCall,
6758
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
6859
SDNPVariadic]>;
60+
def riscv_tail : RVSDNode<"TAIL", SDT_RISCVCall,
61+
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
62+
SDNPVariadic]>;
63+
64+
// Software guarded calls for large code model
6965
def riscv_sw_guarded_call : RVSDNode<"SW_GUARDED_CALL", SDT_RISCVCall,
7066
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
7167
SDNPVariadic]>;
68+
def riscv_sw_guarded_tail : RVSDNode<"SW_GUARDED_TAIL", SDT_RISCVCall,
69+
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
70+
SDNPVariadic]>;
71+
7272
def riscv_ret_glue : RVSDNode<"RET_GLUE", SDTNone,
7373
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
7474
def riscv_sret_glue : RVSDNode<"SRET_GLUE", SDTNone,
@@ -77,40 +77,78 @@ def riscv_mret_glue : RVSDNode<"MRET_GLUE", SDTNone,
7777
[SDNPHasChain, SDNPOptInGlue]>;
7878
def riscv_mileaveret_glue : RVSDNode<"QC_C_MILEAVERET_GLUE", SDTNone,
7979
[SDNPHasChain, SDNPOptInGlue]>;
80+
81+
// Select with condition operator - This selects between a true value and
82+
// a false value (ops #3 and #4) based on the boolean result of comparing
83+
// the lhs and rhs (ops #0 and #1) of a conditional expression with the
84+
// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
85+
// The lhs and rhs are XLenVT integers. The true and false values can be
86+
// integer or floating point.
8087
def riscv_selectcc : RVSDNode<"SELECT_CC", SDT_RISCVSelectCC>;
8188
def riscv_brcc : RVSDNode<"BR_CC", SDT_RISCVBrCC,
8289
[SDNPHasChain]>;
83-
def riscv_tail : RVSDNode<"TAIL", SDT_RISCVCall,
84-
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
85-
SDNPVariadic]>;
86-
def riscv_sw_guarded_tail : RVSDNode<"SW_GUARDED_TAIL", SDT_RISCVCall,
87-
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
88-
SDNPVariadic]>;
90+
91+
// Software guarded BRIND node. Operand is the target address.
8992
def riscv_sw_guarded_brind : RVSDNode<"SW_GUARDED_BRIND",
9093
SDTBrind, [SDNPHasChain]>;
94+
95+
// RV64I shifts, directly matching the semantics of the named RISC-V
96+
// instructions.
9197
def riscv_sllw : RVSDNode<"SLLW", SDT_RISCVIntBinOpW>;
9298
def riscv_sraw : RVSDNode<"SRAW", SDT_RISCVIntBinOpW>;
9399
def riscv_srlw : RVSDNode<"SRLW", SDT_RISCVIntBinOpW>;
94-
def riscv_read_csr : RVSDNode<"READ_CSR", SDT_RISCVReadCSR,
100+
101+
// Reads value of CSR. The first operand is the address of the required CSR.
102+
// The result is the read value.
103+
def riscv_read_csr : RVSDNode<"READ_CSR",
104+
SDTypeProfile<1, 1, [SDTCisInt<0>,
105+
SDTCisInt<1>]>,
95106
[SDNPHasChain]>;
96-
def riscv_write_csr : RVSDNode<"WRITE_CSR", SDT_RISCVWriteCSR,
107+
// Write value to CSR. The first operand is the address of the required CSR,
108+
// the second is the value to write.
109+
def riscv_write_csr : RVSDNode<"WRITE_CSR",
110+
SDTypeProfile<0, 2, [SDTCisInt<0>,
111+
SDTCisInt<1>]>,
97112
[SDNPHasChain]>;
98-
def riscv_swap_csr : RVSDNode<"SWAP_CSR", SDT_RISCVSwapCSR,
113+
114+
// Read and write value of CSR. The first operand is the address of the
115+
// required CSR, the second is the value to write, and the result is the
116+
// read value (before modification).
117+
def riscv_swap_csr : RVSDNode<"SWAP_CSR",
118+
SDTypeProfile<1, 2, [SDTCisInt<0>,
119+
SDTCisInt<1>,
120+
SDTCisInt<2>]>,
99121
[SDNPHasChain]>;
100122

123+
// A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
124+
// It takes a chain operand and another two target constant operands (the
125+
// CSR numbers of the low and high parts of the counter).
101126
def riscv_read_counter_wide : RVSDNode<"READ_COUNTER_WIDE",
102-
SDT_RISCVReadCounterWide,
127+
SDTypeProfile<2, 2, [SDTCisVT<0, i32>,
128+
SDTCisVT<1, i32>,
129+
SDTCisInt<2>,
130+
SDTCisInt<3>]>,
103131
[SDNPHasChain, SDNPSideEffect]>;
104132

133+
// Add the Lo 12 bits from an address. Selected to ADDI.
105134
def riscv_add_lo : RVSDNode<"ADD_LO", SDTIntBinOp>;
135+
136+
// Get the Hi 20 bits from an address. Selected to LUI.
106137
def riscv_hi : RVSDNode<"HI", SDTIntUnaryOp>;
138+
139+
// Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
107140
def riscv_lla : RVSDNode<"LLA", SDTIntUnaryOp>;
141+
142+
// Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
108143
def riscv_add_tprel : RVSDNode<"ADD_TPREL",
109144
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
110145
SDTCisSameAs<0, 2>,
111146
SDTCisSameAs<0, 3>,
112147
SDTCisInt<0>]>>;
113148

149+
// To avoid stack clash, allocation is performed by block and each block is
150+
// probed.
151+
// FIXME: The Type Profile here is incorrect.
114152
def riscv_probed_alloca : RVSDNode<"PROBED_ALLOCA",
115153
SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
116154
SDTCisVT<0, i32>]>,

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,29 +37,55 @@ def SDT_RISCVFSGNJX
3737
def riscv_fclass
3838
: RVSDNode<"FCLASS", SDT_RISCVFCLASS>;
3939

40+
// Rounds an FP value to its corresponding integer in the same FP format.
41+
// First operand is the value to round, the second operand is the largest
42+
// integer that can be represented exactly in the FP format. This will be
43+
// expanded into multiple instructions and basic blocks with a custom
44+
// inserter.
4045
def riscv_fround
4146
: RVSDNode<"FROUND", SDT_RISCVFROUND>;
4247

4348
def riscv_fsgnjx
4449
: RVSDNode<"FSGNJX", SDT_RISCVFSGNJX>;
4550

51+
// FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
52+
// XLEN is the only legal integer width.
53+
//
54+
// FMV_W_X_RV64 matches the semantics of the FMV.W.X.
55+
// FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
56+
//
57+
// This is a more convenient semantic for producing dagcombines that remove
58+
// unnecessary GPR->FPR->GPR moves.
4659
def riscv_fmv_w_x_rv64
4760
: RVSDNode<"FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>;
4861
def riscv_fmv_x_anyextw_rv64
4962
: RVSDNode<"FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>;
63+
64+
// FP to 32 bit int conversions for RV64. These are used to keep track of the
65+
// result being sign extended to 64 bit. These saturate out of range inputs.
66+
// Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
67+
// is passed as a TargetConstant operand using the RISCVFPRndMode enum.
5068
def riscv_fcvt_w_rv64
5169
: RVSDNode<"FCVT_W_RV64", SDT_RISCVFCVT_W_RV64>;
5270
def riscv_fcvt_wu_rv64
5371
: RVSDNode<"FCVT_WU_RV64", SDT_RISCVFCVT_W_RV64>;
72+
73+
// FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
74+
// fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
75+
// range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
76+
// is passed as a TargetConstant operand using the RISCVFPRndMode enum.
5477
def riscv_fcvt_x
5578
: RVSDNode<"FCVT_X", SDT_RISCVFCVT_X>;
5679
def riscv_fcvt_xu
5780
: RVSDNode<"FCVT_XU", SDT_RISCVFCVT_X>;
5881

82+
// Floating point fmax and fmin matching the RISC-V instruction semantics.
5983
def riscv_fmin : RVSDNode<"FMIN", SDTFPBinOp>;
6084
def riscv_fmax : RVSDNode<"FMAX", SDTFPBinOp>;
6185

6286
let IsStrictFP = true in {
87+
// FP to 32 bit int conversions for RV64. These are used to keep track of the
88+
// result being sign extended to 64 bit. These saturate out of range inputs.
6389
def riscv_strict_fcvt_w_rv64
6490
: RVSDNode<"STRICT_FCVT_W_RV64", SDT_RISCVFCVT_W_RV64,
6591
[SDNPHasChain]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoM.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,12 @@
1515
// RISC-V specific DAG Nodes.
1616
//===----------------------------------------------------------------------===//
1717

18+
// Multiply high for signedxunsigned.
1819
def riscv_mulhsu : RVSDNode<"MULHSU", SDTIntBinOp>;
20+
21+
// 32-bit operations from RV64M that can't be simply matched with a pattern
22+
// at instruction selection time. These have undefined behavior for division
23+
// by 0 or overflow (divw) like their target independent counterparts.
1924
def riscv_divw : RVSDNode<"DIVW", SDT_RISCVIntBinOpW>;
2025
def riscv_divuw : RVSDNode<"DIVUW", SDT_RISCVIntBinOpW>;
2126
def riscv_remuw : RVSDNode<"REMUW", SDT_RISCVIntBinOpW>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,13 @@
7070
///
7171
//===----------------------------------------------------------------------===//
7272

73+
// VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
74+
// extended from the vector element size.
7375
def riscv_vmv_x_s : RVSDNode<"VMV_X_S",
7476
SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,
7577
SDTCisInt<1>]>>;
78+
79+
// Read VLENB CSR
7680
def riscv_read_vlenb : RVSDNode<"READ_VLENB",
7781
SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
7882

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