[RFC][Sleigh] Add base implementation for MIPS (WIP)

CMakeLists.txt

@@ -80,6 +80,7 @@ set(REMILL_BUILD_SEMANTICS_DIR_AARCH64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AAr
 set(REMILL_BUILD_SEMANTICS_DIR_SPARC32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC32/Runtime")
 set(REMILL_BUILD_SEMANTICS_DIR_SPARC64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC64/Runtime")
 set(REMILL_BUILD_SEMANTICS_DIR_PPC64_32ADDR "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/PPC/Runtime")
+set(REMILL_BUILD_SEMANTICS_DIR_MIPS64_32ADDR "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/MIPS/Runtime")
 set(REMILL_INCLUDE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/include")
 set(REMILL_LIB_DIR "${CMAKE_CURRENT_SOURCE_DIR}/lib")
 
@@ -220,6 +221,7 @@ target_compile_definitions(remill_settings INTERFACE
   "REMILL_BUILD_SEMANTICS_DIR_SPARC32=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC32}\""
   "REMILL_BUILD_SEMANTICS_DIR_SPARC64=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC64}\""
   "REMILL_BUILD_SEMANTICS_DIR_PPC64_32ADDR=\"${REMILL_BUILD_SEMANTICS_DIR_PPC64_32ADDR}\""
+  "REMILL_BUILD_SEMANTICS_DIR_MIPS64_32ADDR=\"${REMILL_BUILD_SEMANTICS_DIR_MIPS64_32ADDR}\""
 )
 
 set(ghidra_patch_user "github-actions[bot]")
@@ -254,8 +256,17 @@ sleigh_compile(
   OUT_FILE "${sleigh_BINARY_DIR}/specfiles/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.sla"
 )
 
+sleigh_compile(
+  TARGET mips_be_vr4300_spec
+  COMPILER "${sleigh_compiler}"
+  SLASPEC "${ghidra-fork_SOURCE_DIR}/Ghidra/Processors/MIPS/data/languages/mips64be.slaspec"
+  LOG_FILE "${sleigh_BINARY_DIR}/sleighspecs/spec_build_logs/mips64be.sla.log"
+  OUT_FILE "${sleigh_BINARY_DIR}/specfiles/Ghidra/Processors/MIPS/data/languages/mips64be.sla"
+)
+
 add_custom_target(sleigh_custom_specs)
 add_dependencies(sleigh_custom_specs ppc_e200_spec)
+add_dependencies(sleigh_custom_specs mips_be_vr4300_spec)
 
 target_link_libraries(remill_settings INTERFACE
   ${llvm_libs}
@@ -317,6 +328,7 @@ if(REMILL_ENABLE_INSTALL_TARGET)
   )
 
   install(FILES "${sleigh_BINARY_DIR}/specfiles/Ghidra/Processors/PowerPC/data/languages/ppc_32_e200_be.sla" DESTINATION "${CMAKE_INSTALL_DATADIR}/sleigh/specfiles/Ghidra/Processors/PowerPC/data/languages/")
+  install(FILES "${sleigh_BINARY_DIR}/specfiles/Ghidra/Processors/MIPS/data/languages/mips64be.sla" DESTINATION "${CMAKE_INSTALL_DATADIR}/sleigh/specfiles/Ghidra/Processors/MIPS/data/languages/")
 
   configure_file(
     "${CMAKE_CURRENT_SOURCE_DIR}/cmake/remillConfig.cmake.in"

include/remill/Arch/Arch.h

@@ -357,6 +357,7 @@ class Arch {
   bool IsSPARC32(void) const;
   bool IsSPARC64(void) const;
   bool IsPPC(void) const;
+  bool IsMIPS(void) const;
 
   bool IsWindows(void) const;
   bool IsLinux(void) const;
@@ -437,6 +438,10 @@ class Arch {
   static ArchPtr GetSleighPPC(llvm::LLVMContext *context, OSName os,
                               ArchName arch_name);
 
+  // Defined in `lib/Arch/Sleigh/MIPSArch.cpp`
+  static ArchPtr GetSleighMIPS(llvm::LLVMContext *context, OSName os,
+                              ArchName arch_name);
+
   // Defined in `lib/Arch/SPARC32/Arch.cpp`.
   static ArchPtr GetSPARC32(llvm::LLVMContext *context, OSName os,
                           ArchName arch_name);

include/remill/Arch/MIPS/Runtime/State.h

@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2022-present Trail of Bits, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#pragma clang diagnostic push
+#pragma clang diagnostic fatal "-Wpadded"
+
+#include "remill/Arch/Runtime/State.h"
+
+#if !defined(INCLUDED_FROM_REMILL)
+#  include "remill/Arch/Runtime/Types.h"
+#endif
+
+struct Reg final {
+  union {
+    alignas(4) uint32_t dword;
+    alignas(8) uint64_t qword;
+  } __attribute__((packed));
+} __attribute__((packed));
+
+static_assert(sizeof(uint64_t) == sizeof(Reg), "Invalid packing of `Reg`.");
+static_assert(0 == __builtin_offsetof(Reg, dword),
+              "Invalid packing of `Reg::dword`.");
+
+static_assert(0 == __builtin_offsetof(Reg, qword),
+              "Invalid packing of `Reg::qword`.");
+
+// General Purpose Registers
+struct alignas(8) GPR final {
+  volatile uint64_t _0;
+  Reg zero;
+  volatile uint64_t _1;
+  Reg at;
+  volatile uint64_t _2;
+  Reg v0;
+  volatile uint64_t _3;
+  Reg v1;
+  volatile uint64_t _4;
+  Reg a0;
+  volatile uint64_t _5;
+  Reg a1;
+  volatile uint64_t _6;
+  Reg a2;
+  volatile uint64_t _7;
+  Reg a3;
+  volatile uint64_t _8;
+  Reg t0;
+  volatile uint64_t _9;
+  Reg t1;
+  volatile uint64_t _10;
+  Reg t2;
+  volatile uint64_t _11;
+  Reg t3;
+  volatile uint64_t _12;
+  Reg t4;
+  volatile uint64_t _13;
+  Reg t5;
+  volatile uint64_t _14;
+  Reg t6;
+  volatile uint64_t _15;
+  Reg t7;
+  volatile uint64_t _16;
+  Reg s0;
+  volatile uint64_t _17;
+  Reg s1;
+  volatile uint64_t _18;
+  Reg s2;
+  volatile uint64_t _19;
+  Reg s3;
+  volatile uint64_t _20;
+  Reg s4;
+  volatile uint64_t _21;
+  Reg s5;
+  volatile uint64_t _22;
+  Reg s6;
+  volatile uint64_t _23;
+  Reg s7;
+  volatile uint64_t _24;
+  Reg t8;
+  volatile uint64_t _25;
+  Reg t9;
+  volatile uint64_t _26;
+  Reg k0;
+  volatile uint64_t _27;
+  Reg k1;
+  volatile uint64_t _28;
+  Reg gp;
+  volatile uint64_t _29;
+  Reg sp;
+  volatile uint64_t _30;
+  Reg s8;
+  volatile uint64_t _31;
+  Reg ra;
+  volatile uint64_t _32;
+  Reg pc;
+
+} __attribute__((packed));
+
+static_assert(528 == sizeof(GPR), "Invalid structure packing of `GPR`.");
+
+// Floating Pointer Registers
+struct alignas(8) FPR final {
+  volatile uint64_t _0;
+  Reg f0;
+  volatile uint64_t _1;
+  Reg f1;
+  volatile uint64_t _2;
+  Reg f2;
+  volatile uint64_t _3;
+  Reg f3;
+  volatile uint64_t _4;
+  Reg f4;
+  volatile uint64_t _5;
+  Reg f5;
+  volatile uint64_t _6;
+  Reg f6;
+  volatile uint64_t _7;
+  Reg f7;
+  volatile uint64_t _8;
+  Reg f8;
+  volatile uint64_t _9;
+  Reg f9;
+  volatile uint64_t _10;
+  Reg f10;
+  volatile uint64_t _11;
+  Reg f11;
+  volatile uint64_t _12;
+  Reg f12;
+  volatile uint64_t _13;
+  Reg f13;
+  volatile uint64_t _14;
+  Reg f14;
+  volatile uint64_t _15;
+  Reg f15;
+  volatile uint64_t _16;
+  Reg f16;
+  volatile uint64_t _17;
+  Reg f17;
+  volatile uint64_t _18;
+  Reg f18;
+  volatile uint64_t _19;
+  Reg f19;
+  volatile uint64_t _20;
+  Reg f20;
+  volatile uint64_t _21;
+  Reg f21;
+  volatile uint64_t _22;
+  Reg f22;
+  volatile uint64_t _23;
+  Reg f23;
+  volatile uint64_t _24;
+  Reg f24;
+  volatile uint64_t _25;
+  Reg f25;
+  volatile uint64_t _26;
+  Reg f26;
+  volatile uint64_t _27;
+  Reg f27;
+  volatile uint64_t _28;
+  Reg f28;
+  volatile uint64_t _29;
+  Reg f29;
+  volatile uint64_t _30;
+  Reg f30;
+  volatile uint64_t _31;
+  Reg f31;
+
+} __attribute__((packed));
+
+static_assert(512 == sizeof(FPR), "Invalid structure packing of `FPR`.");
+
+struct alignas(8) FlagRegisters final {
+  volatile uint64_t _0;
+  Reg ISAModeSwitch;
+} __attribute__((packed));
+
+struct alignas(8) COP0Registers final {
+  volatile uint64_t _0;
+  Reg Index;
+  volatile uint64_t _1;
+  Reg Random;
+  volatile uint64_t _2;
+  Reg EntryLo0;
+  volatile uint64_t _3;
+  Reg EntryLo1;
+  volatile uint64_t _4;
+  Reg Context;
+  volatile uint64_t _5;
+  Reg PageMask;
+  volatile uint64_t _6;
+  Reg Wired;
+  volatile uint64_t _7;
+  Reg HWREna;
+  volatile uint64_t _8;
+  Reg BadVAddr;
+  volatile uint64_t _9;
+  Reg Count;
+  volatile uint64_t _10;
+  Reg EntryHi;
+  volatile uint64_t _11;
+  Reg Compare;
+  volatile uint64_t _12;
+  Reg Status;
+  volatile uint64_t _13;
+  Reg Cause;
+  volatile uint64_t _14;
+  Reg EPC;
+  volatile uint64_t _15;
+  Reg PRId;
+  volatile uint64_t _16;
+  Reg Config;
+  volatile uint64_t _17;
+  Reg LLAddr;
+  volatile uint64_t _18;
+  Reg WatchLo;
+  volatile uint64_t _19;
+  Reg WatchHi;
+  volatile uint64_t _20;
+  Reg XContext;
+  volatile uint64_t _21;
+  Reg cop0_reg21;
+  volatile uint64_t _22;
+  Reg cop0_reg22;
+  volatile uint64_t _23;
+  Reg Debug;
+  volatile uint64_t _24;
+  Reg DEPC;
+  volatile uint64_t _25;
+  Reg PerfCnt;
+  volatile uint64_t _26;
+  Reg ErrCtl;
+  volatile uint64_t _27;
+  Reg CacheErr;
+  volatile uint64_t _28;
+  Reg TagLo;
+  volatile uint64_t _29;
+  Reg TagHi;
+  volatile uint64_t _30;
+  Reg ErrorEPC;
+  volatile uint64_t _31;
+  Reg DESAVE;
+} __attribute__((packed));
+
+struct alignas(8) MIPSState : public ArchState {
+  GPR gpr;  // 528 bytes.
+
+  uint64_t _0;
+
+  FPR fpr;
+
+  uint64_t _1;
+
+  FlagRegisters flags;
+
+  uint64_t _2;
+
+  COP0Registers cop0;
+
+  uint64_t _3;
+} __attribute__((packed));
+
+struct State : public MIPSState {};
+
+#pragma clang diagnostic pop

include/remill/Arch/Name.h

@@ -121,6 +121,7 @@ enum ArchName : uint32_t {
   kArchThumb2LittleEndian,
 
   kArchPPC,
+  kArchMIPS,
 };
 
 ArchName GetArchName(const llvm::Triple &triple);

include/remill/Arch/Runtime/HyperCall.h

@@ -96,6 +96,9 @@ class SyncHyperCall {
 
     kPPCEmulateInstruction,
     kPPCSysCall,
+
+    kMIPSEmulateInstruction,
+    kMIPSSysCall,
   };
 } __attribute__((packed));
 

include/remill/Arch/Runtime/Intrinsics.h

@@ -425,4 +425,8 @@ __remill_ppc_emulate_instruction(Memory *);
 
 [[gnu::used, gnu::const]] extern Memory *__remill_ppc_syscall(Memory *);
 
+[[gnu::used, gnu::const]] extern Memory *__remill_mips_emulate_instruction(Memory *);
+
+[[gnu::used, gnu::const]] extern Memory *__remill_mips_syscall(Memory *);
+
 }  // extern C