Add sc8280xp camcc

Signed-off-by: Bryan O'Donoghue <[email protected]>

Author: 0xB0D

sc8280xp.c

@@ -62,6 +62,26 @@ static struct gcc_mux gcc = {
 	.debug_status_reg = 0x6203c,
 };
 
+static struct debug_mux cam_cc = {
+	.phys = 0xad00000,
+	.size = 0x20000,
+	.block_name = "camcc",
+
+	.measure = measure_leaf,
+	.parent = &gcc.mux,
+	.parent_mux_val = 0x70,
+
+	.enable_reg = 0xd008,
+	.enable_mask = BIT(0),
+
+	.mux_reg = 0xd100,
+	.mux_mask = 0xff,
+
+	.div_reg = 0xd004,
+	.div_mask = 0x0f,
+	.div_val = 2,
+};
+
 static struct debug_mux disp0_cc = {
 	.phys = 0xaf00000,
 	.size = 0x20000,
@@ -439,6 +459,99 @@ static struct measure_clk sc8280xp_clocks[] = {
 	{ "disp1_cc_sleep_clk",					&disp1_cc, 0x46 },
 	{ "disp1_cc_xo_clk",					&disp1_cc, 0x45 },
 	{ "measure_only_mccc_clk", 				&mc_cc, 0x50 },
+	{ "cam_cc_mclk0_clk",					&cam_cc, 0x1 },
+	{ "cam_cc_mclk1_clk",					&cam_cc, 0x2 },
+	{ "cam_cc_mclk2_clk",					&cam_cc, 0x3 },
+	{ "cam_cc_mclk3_clk",					&cam_cc, 0x4 },
+	{ "cam_cc_csi0phytimer_clk",				&cam_cc, 0x5 },
+	{ "cam_cc_csiphy0_clk",					&cam_cc, 0x6},
+	{ "cam_cc_csi1phytimer_clk",				&cam_cc, 0x7},
+	{ "cam_cc_csiphy1_clk",					&cam_cc, 0x8},
+	{ "cam_cc_csi2phytimer_clk",				&cam_cc, 0x9},
+	{ "cam_cc_csiphy2_clk",					&cam_cc, 0xa},
+	{ "cam_cc_bps_clk",					&cam_cc, 0xb},
+	{ "cam_cc_bps_axi_clk",					&cam_cc, 0xc},
+	{ "cam_cc_bps_areg_clk",				&cam_cc, 0xd},
+	{ "cam_cc_bps_ahb_clk",					&cam_cc, 0xe},
+	{ "cam_cc_ipe_0_clk",					&cam_cc, 0xf},
+	{ "cam_cc_ipe_0_axi_clk",				&cam_cc, 0x10},
+	{ "cam_cc_ipe_0_areg_clk",				&cam_cc, 0x11},
+	{ "cam_cc_ipe_0_ahb_clk",				&cam_cc, 0x12},
+	{ "cam_cc_ipe_1_clk",					&cam_cc, 0x13},
+	{ "cam_cc_ipe_1_axi_clk",				&cam_cc, 0x14},
+	{ "cam_cc_ipe_1_areg_clk",				&cam_cc, 0x15},
+	{ "cam_cc_ipe_1_ahb_clk",				&cam_cc, 0x16},
+	{ "cam_cc_ife_0_clk",					&cam_cc, 0x17},
+	{ "cam_cc_ife_0_dsp_clk",				&cam_cc, 0x18},
+	{ "cam_cc_ife_0_csid_clk",				&cam_cc, 0x19},
+	{ "cam_cc_ife_0_cphy_rx_clk",				&cam_cc, 0x1a},
+	{ "cam_cc_ife_0_axi_clk",				&cam_cc, 0x1b},
+	{ "cam_cc_spdm_ife_1_clk",				&cam_cc, 0x1c},
+	{ "cam_cc_ife_1_clk",					&cam_cc, 0x1d},
+	{ "cam_cc_ife_1_dsp_clk",				&cam_cc, 0x1e},
+	{ "cam_cc_ife_1_csid_clk",				&cam_cc, 0x1f},
+	{ "cam_cc_ife_1_cphy_rx_clk",				&cam_cc, 0x20},
+	{ "cam_cc_ife_1_axi_clk",				&cam_cc, 0x21},
+	{ "cam_cc_ife_lite_0_clk",				&cam_cc, 0x22},
+	{ "cam_cc_ife_lite_0_csid_clk",				&cam_cc, 0x23},
+	{ "cam_cc_ife_lite_0_cphy_rx_clk",			&cam_cc, 0x24},
+	{ "cam_cc_jpeg_clk",					&cam_cc, 0x25},
+	{ "cam_cc_icp_clk",					&cam_cc, 0x26},
+	{ "cam_cc_camnoc_axi_clk",				&cam_cc, 0x27},
+	{ "cam_cc_spdm_ife_1_csid_clk",				&cam_cc, 0x28},
+	{ "cam_cc_pll_lock_monitor_clk",			&cam_cc, 0x29},
+	{ "cam_cc_cci_0_clk",					&cam_cc, 0x2a},
+	{ "cam_cc_lrme_clk",					&cam_cc, 0x2b},
+	{ "cam_cc_cpas_ahb_clk",				&cam_cc, 0x2c},
+	{ "cam_cc_spdm_bps_clk",				&cam_cc, 0x2d},
+	{ "cam_cc_core_ahb_clk",				&cam_cc, 0x2e},
+	{ "cam_cc_spdm_ipe_0_clk",				&cam_cc, 0x2f},
+	{ "cam_cc_spdm_ipe_1_clk",				&cam_cc, 0x30},
+	{ "cam_cc_spdm_ife_0_clk",				&cam_cc, 0x31},
+	{ "cam_cc_spdm_ife_0_csid_clk",				&cam_cc, 0x32},
+	{ "cam_cc_camnoc_dcd_xo_clk",				&cam_cc, 0x33},
+	{ "cam_cc_spdm_jpeg_clk",				&cam_cc, 0x34},
+	{ "cam_cc_csi3phytimer_clk",				&cam_cc, 0x35},
+	{ "cam_cc_csiphy3_clk",					&cam_cc, 0x36},
+	{ "cam_cc_icp_ahb_clk",					&cam_cc, 0x37},
+	{ "cam_cc_ife_lite_1_clk",				&cam_cc, 0x38},
+	{ "cam_cc_ife_lite_1_csid_clk",				&cam_cc, 0x39},
+	{ "cam_cc_ife_lite_1_cphy_rx_clk",			&cam_cc, 0x3a},
+	{ "cam_cc_cci_1_clk",					&cam_cc, 0x3b},
+	{ "cam_cc_gdsc_clk",					&cam_cc, 0x3c},
+	{ "cam_cc_qdss_debug_clk",				&cam_cc, 0x3d},
+	{ "cam_cc_qdss_debug_xo_clk",				&cam_cc, 0x3e},
+	{ "cam_cc_sleep_clk",					&cam_cc, 0x3f},
+	{ "csiphy0_cam_cc_debug_clk",				&cam_cc, 0x40},
+	{ "csiphy1_cam_cc_debug_clk",				&cam_cc, 0x41},
+	{ "csiphy2_cam_cc_debug_clk",				&cam_cc, 0x42},
+	{ "csiphy3_cam_cc_debug_clk",				&cam_cc, 0x43},
+	{ "cam_cc_ife_2_clk",					&cam_cc, 0x44},
+	{ "cam_cc_spdm_ife_2_clk",				&cam_cc, 0x45},
+	{ "cam_cc_ife_2_dsp_clk",				&cam_cc, 0x46},
+	{ "cam_cc_ife_2_csid_clk",				&cam_cc, 0x47},
+	{ "cam_cc_spdm_ife_2_csid_clk",				&cam_cc, 0x48},
+	{ "cam_cc_ife_2_cphy_rx_clk",				&cam_cc, 0x49},
+	{ "cam_cc_ife_2_axi_clk",				&cam_cc, 0x4a},
+	{ "cam_cc_ife_3_clk",					&cam_cc, 0x4b},
+	{ "cam_cc_spdm_ife_3_clk",				&cam_cc, 0x4c},
+	{ "cam_cc_ife_3_dsp_clk",				&cam_cc, 0x4d},
+	{ "cam_cc_ife_3_csid_clk",				&cam_cc, 0x4e},
+	{ "cam_cc_spdm_ife_3_csid_clk",				&cam_cc, 0x4f},
+	{ "cam_cc_ife_3_cphy_rx_clk",				&cam_cc, 0x50},
+	{ "cam_cc_ife_3_axi_clk",				&cam_cc, 0x51},
+	{ "cam_cc_ife_lite_2_clk",				&cam_cc, 0x55},
+	{ "cam_cc_ife_lite_2_csid_clk",				&cam_cc, 0x56},
+	{ "cam_cc_ife_lite_2_cphy_rx_clk",			&cam_cc, 0x57},
+	{ "cam_cc_ife_lite_3_clk",				&cam_cc, 0x58},
+	{ "cam_cc_ife_lite_3_csid_clk",				&cam_cc, 0x59},
+	{ "cam_cc_ife_lite_3_cphy_rx_clk",			&cam_cc, 0x5a},
+	{ "cam_cc_cci_2_clk",					&cam_cc, 0x5b},
+	{ "cam_cc_cci_3_clk",					&cam_cc, 0x5c},
+	{ "cam_cc_mclk4_clk",					&cam_cc, 0x5d},
+	{ "cam_cc_mclk5_clk",					&cam_cc, 0x5e},
+	{ "cam_cc_mclk6_clk",					&cam_cc, 0x5f},
+	{ "cam_cc_mclk7_clk",					&cam_cc, 0x60},
 	{}
 };