Expanded support for CFUs.#14

Draft

tcal-x wants to merge 34 commits intolitex-hub:masterfrom

tcal-x:fomu-cfu-mm2

Commits on Nov 5, 2020

Changes to build VexRiscv versions with Cfu plugin:
Tim Callahan
committed
Set up wrappers to contain the cpu+cfu.
Tim Callahan
committed
Add 'clk' input to CFU modules.
Tim Callahan
committed
Add perf count CSRs; rebuild CFU VexRiscv Verilogs.
Tim Callahan
committed

Commits on Jan 7, 2021

Increase to 8 perf counter CSRs; rebuild.
Tim Callahan
committed

Commits on Jan 12, 2021

Bump both I$, D$ from 4k to 8k.
Tim Callahan
committed

Commits on Feb 19, 2021

Bump SpinalHdl/VexRiscv submodules; rebuild; widen CFU funcid port.
Tim Callahan
committed

Commits on Mar 5, 2021

Delete SpinalHDL submodule.
Tim Callahan
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Commits on Mar 6, 2021

Rebuild: VexRiscv master w/ cfu fix, Spinal 1.4.3, wide func_id.
Tim Callahan
committed

Commits on Apr 7, 2021

Update CFU instr. encoding to match spec (update vex submodule too).
Tim Callahan
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Match CFU spec; function_id now 10b {funct7,funct3}.
Tim Callahan
committed

Commits on Apr 8, 2021

Remove I-format CFU instruction; it impacts timing.
Tim Callahan
committed

Commits on Apr 25, 2021

Add 'SlimCfu' variants; add missing reset/rst connections.
Tim Callahan
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Commits on Apr 29, 2021

Slim: reduce Icache size to 1kB.
Tim Callahan
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Rebuild SlimCfu CPUs w/ 1kB Icache.
Tim Callahan
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Commits on Jun 3, 2021

Remove wrapper mechanism for VexRiscv/CFU.
Tim Callahan
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Rebuild Verilogs at hash e78ff1c.
Tim Callahan
committed

Commits on Jun 11, 2021

Add VexRiscv for Fomu -- minimal, plus hard muldiv, plus mcycle.
Tim Callahan
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Trim Fomu variants by removing alignment etc. checks.
Tim Callahan
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Commits on Jul 19, 2021

Tweak the Fomu variant to remove division, debug, and writeback/memory stages.
JosephBushagour
committed

Commits on Jul 20, 2021

Merge pull request #1 from JosephBushagour/jbushagour_fomu_tweaks
tcal-x
authored

Commits on Aug 2, 2021

Commits on Aug 9, 2021

Commits on Aug 31, 2021

New "perf" variant has perfCSRs.
Tim Callahan
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Rebuild affected verilogs with correct hash comment (5bb9114).
Tim Callahan
committed

Commits on Sep 16, 2021

Add slimperf+cfu variant.
Tim Callahan
committed

Commits on Sep 21, 2021

Merge branch 'master' into fomu-cfu-mm2
Tim Callahan
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Rebuild Verilogs at 593e180.
Tim Callahan
committed

Commits on Sep 29, 2021

Add 'slim' variant for completeness.
Tim Callahan
committed

Commits on Sep 30, 2021

Rebuild VexRiscv_Slim.v so it has correct hash in comment.
Tim Callahan
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Remove performance CSRs from 'FullCfu' variants.
Tim Callahan
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Rebuild VexRiscv_FullCfu*.v at 7454d1ac.
Tim Callahan
committed