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3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -52,3 +52,6 @@
[submodule "third_party/litei2c"]
path = third_party/litei2c
url = https://github.com/litex-hub/litei2c
[submodule "third_party/litesdcard"]
path = third_party/litesdcard
url = https://github.com/enjoy-digital/litesdcard.git
2 changes: 2 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,8 @@ Build options
| --sys-clk-freq | System clock frequency |
| --with_spi | Enable SPI |
| --with_spi_flash | Enable SPI flash |
| --with-sdcard | Enable SD card via [LiteSDCard](https://github.com/enjoy-digital/litesdcard) |
| --sdcard-adapter | Select SD card PMOD adapter |
| --with_i2c | Enable I2C (bitbang driver) |
| --with_litei2c | Enable I2C via [LiteI2C](https://github.com/litex-hub/litei2c) |
| --with_pwm | Enable PWM |
Expand Down
2 changes: 1 addition & 1 deletion init
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
export PATH="${PWD}/third_party/litex/litex/tools:$PATH"
export PATH="${PWD}/tools/conda/bin:$PATH"

directories=(litedram liteeth litei2c liteiclink litepcie litespi litesata litescope litevideo litex litex-boards litex-renode migen nmigen pythondata-cpu-vexriscv pythondata-software-compiler_rt pythondata-software-picolibc)
directories=(litedram liteeth litei2c liteiclink litepcie litespi litesata litesdcard litescope litevideo litex litex-boards litex-renode migen nmigen pythondata-cpu-vexriscv pythondata-software-compiler_rt pythondata-software-picolibc)

for directory in "${directories[@]}";
do
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7 changes: 7 additions & 0 deletions make.py
Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,8 @@ def main():
parser.add_argument("--spi-data-width", type=int, default=8, help="SPI data width (maximum transfered bits per xfer, Arty target only)")
parser.add_argument("--spi-clk-freq", type=int, default=1e6, help="SPI clock frequency (Arty target only)")
parser.add_argument("--spi_flash_rate", default="1:1", help="SPI flash rate, can be 1:1 or 1:2 (Arty target only)")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--sdcard-adapter", default="digilent", help="SDCard PMOD adapter (digilent or numato).")
parser.add_argument("--with_mmcm", action="store_true", help="Enable mmcm (Arty target only)")
parser.add_argument("--with_watchdog", action="store_true", help="Enable watchdog")
parser.add_argument("--watchdog_width", type=int, default=32, help="Watchdog width")
Expand All @@ -106,6 +108,7 @@ def main():
args.with_pwm = True
args.with_mmcm = True
args.with_watchdog = True
args.with_sdcard = True

if args.board == "all":
board_names = list(supported_boards.keys())
Expand Down Expand Up @@ -163,6 +166,10 @@ def main():
print("Adding mmcm implicitly, cause i2s core needs special clk signals")
soc.add_mmcm(board.mmcm_freq)
soc.add_i2s()
if args.with_sdcard:
from litex_boards.platforms import digilent_arty
soc.platform.add_extension(digilent_arty._numato_sdcard_pmod_io if args.sdcard_adapter == "numato" else digilent_arty._sdcard_pmod_io)
soc.add_sdcard()

build_dir = os.path.join("build", board.bitstream_name)

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3 changes: 2 additions & 1 deletion soc_zephyr.py
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,6 @@ class _SoCZephyr(soc_cls):
"spi": 4, # addr: 0xe0002000
"timer0": 5, # addr: 0xe0002800
"sdram": 6, # addr: 0xe0003000
"uartphy": 7, # addr: 0xe0004000
"mmcm": 9, # addr: 0xe0004800
"i2c0": 10, # addr: 0xe0005000
"rgb_led_r0": 14, # addr: 0xe0007000
Expand All @@ -52,12 +51,14 @@ class _SoCZephyr(soc_cls):
"spiflash": 24, # addr: 0xe000c000
"watchdog0": 26, # addr: 0xe000d000
"litei2c": 27, # addr: 0xe000d800
"sdcard": 29, # addr: 0xe000e000
}}

interrupt_map = {**soc_cls.interrupt_map, **{
"timer0": 1,
"uart": 2,
"ethmac": 3,
"sdcard": 5,
"i2s_rx": 6,
"i2s_tx": 7,
"watchdog0": 8,
Expand Down
2 changes: 1 addition & 1 deletion third_party/litedram
Submodule litedram updated 1 files
+1 −1 setup.py
2 changes: 1 addition & 1 deletion third_party/litesata
Submodule litesata updated 1 files
+1 −1 setup.py
2 changes: 1 addition & 1 deletion third_party/litescope
Submodule litescope updated 1 files
+1 −1 setup.py
1 change: 1 addition & 0 deletions third_party/litesdcard
Submodule litesdcard added at fba767
2 changes: 1 addition & 1 deletion third_party/litex
Submodule litex updated 84 files
+143 −0 CHANGES.md
+172 −35 litex/build/altera/common.py
+1 −1 litex/build/altera/platform.py
+18 −7 litex/build/altera/quartus.py
+58 −16 litex/build/colognechip/common.py
+0 −1 litex/build/colognechip/peppercorn.py
+224 −28 litex/build/efinix/common.py
+12 −4 litex/build/efinix/dbparser.py
+13 −19 litex/build/efinix/ifacewriter.py
+2 −1 litex/build/generic_platform.py
+1 −1 litex/build/generic_toolchain.py
+5 −2 litex/build/gowin/common.py
+1 −3 litex/build/gowin/gowin.py
+35 −21 litex/build/io.py
+38 −2 litex/build/lattice/common.py
+1 −1 litex/build/lattice/oxide.py
+8 −2 litex/build/lattice/radiant.py
+5 −1 litex/build/lattice/trellis.py
+4 −2 litex/build/sim/core/Makefile
+1 −1 litex/build/sim/core/modules/clocker/clocker.c
+2 −2 litex/build/sim/core/modules/spdeeprom/spdeeprom.c
+47 −1 litex/build/sim/core/veril.cpp
+1 −1 litex/build/sim/core/veril.h
+19 −9 litex/build/sim/verilator.py
+13 −2 litex/build/vhd2v_converter.py
+8 −5 litex/build/xilinx/common.py
+4 −2 litex/build/xilinx/platform.py
+65 −4 litex/build/xilinx/vivado.py
+29 −20 litex/gen/fhdl/memory.py
+4 −0 litex/soc/cores/clock/__init__.py
+23 −17 litex/soc/cores/clock/efinix.py
+428 −0 litex/soc/cores/clock/intel_agilex.py
+7 −4 litex/soc/cores/code_8b10b.py
+38 −12 litex/soc/cores/cpu/coreblocks/core.py
+2 −2 litex/soc/cores/cpu/naxriscv/core.py
+8 −2 litex/soc/cores/cpu/vexiiriscv/core.py
+40 −1 litex/soc/cores/cpu/vexiiriscv/system.h
+298 −3 litex/soc/cores/cpu/zynq7000/core.py
+2 −0 litex/soc/cores/dma.py
+8 −9 litex/soc/cores/prbs.py
+26 −12 litex/soc/cores/ram/efinix_hyperram.py
+4 −3 litex/soc/cores/uart.py
+8 −3 litex/soc/cores/video.py
+2 −1 litex/soc/doc/__init__.py
+10 −6 litex/soc/doc/csr.py
+1 −0 litex/soc/integration/builder.py
+15 −11 litex/soc/integration/export.py
+133 −102 litex/soc/integration/soc.py
+3 −2 litex/soc/integration/soc_core.py
+3 −1 litex/soc/interconnect/ahb.py
+48 −4 litex/soc/interconnect/axi/axi_common.py
+54 −32 litex/soc/interconnect/axi/axi_full.py
+124 −76 litex/soc/interconnect/axi/axi_lite.py
+14 −4 litex/soc/interconnect/wishbone.py
+11 −6 litex/soc/software/bios/boot.c
+7 −0 litex/soc/software/bios/boot.h
+1 −1 litex/soc/software/bios/cmds/cmd_bios.c
+1 −1 litex/soc/software/bios/cmds/cmd_boot.c
+20 −0 litex/soc/software/bios/cmds/cmd_liteeth.c
+5 −5 litex/soc/software/bios/cmds/cmd_litesdcard.c
+9 −2 litex/soc/software/bios/main.c
+19 −4 litex/soc/software/bios/readline.c
+3 −0 litex/soc/software/bios/readline.h
+15 −0 litex/soc/software/bios/readline_simple.c
+29 −18 litex/soc/software/include/hw/common.h
+33 −0 litex/soc/software/include/system.h
+2 −0 litex/soc/software/libbase/isr.c
+5 −5 litex/soc/software/libbase/memtest.c
+14 −8 litex/soc/software/libbase/uart.c
+11 −11 litex/soc/software/liblitedram/sdram.c
+4 −4 litex/soc/software/liblitedram/sdram_dbg.c
+191 −5 litex/soc/software/libliteeth/udp.c
+2 −0 litex/soc/software/libliteeth/udp.h
+38 −37 litex/soc/software/liblitesdcard/sdcard.c
+7 −2 litex/soc/software/liblitesdcard/sdcard.h
+13 −4 litex/soc/software/liblitespi/spiflash.c
+2 −2 litex/soc/software/liblitespi/spiram.c
+18 −14 litex/tools/litex_json2dts_linux.py
+3 −28 litex/tools/litex_json2dts_zephyr.py
+8 −7 litex/tools/litex_sim.py
+6 −3 litex/tools/litex_term.py
+25 −10 litex/tools/remote/comm_pcie.py
+80 −14 litex_setup.py
+1 −1 setup.py
2 changes: 1 addition & 1 deletion third_party/litex-boards
Submodule litex-boards updated 78 files
+5 −5 .github/workflows/ci.yml
+20 −4 CONTRIBUTORS
+1 −1 LICENSE
+13 −3 README.md
+427 −0 litex_boards/platforms/alibaba_vu13p.py
+2 −2 litex_boards/platforms/aliexpress_xc7k70t.py
+7 −5 litex_boards/platforms/alinx_ax7010.py
+130 −0 litex_boards/platforms/alinx_ax7020.py
+151 −0 litex_boards/platforms/alinx_ax7203.py
+178 −0 litex_boards/platforms/arrow_axe5000.py
+9 −8 litex_boards/platforms/berkeleylab_marble.py
+247 −0 litex_boards/platforms/berkeleylab_obsidian.py
+68 −0 litex_boards/platforms/bochenjingxin_kintex7_basec.py
+21 −4 litex_boards/platforms/colognechip_gatemate_evb.py
+4 −4 litex_boards/platforms/colorlight_5a_75b.py
+110 −4 litex_boards/platforms/colorlight_5a_75e.py
+3 −4 litex_boards/platforms/digilent_arty.py
+19 −0 litex_boards/platforms/digilent_nexys_video.py
+129 −2 litex_boards/platforms/efinix_ti375_c529_dev_kit.py
+224 −0 litex_boards/platforms/efinix_tz170_j484_dev_kit.py
+210 −0 litex_boards/platforms/hyvision_pcie_opt01_revf.py
+143 −0 litex_boards/platforms/icepi_zero.py
+107 −0 litex_boards/platforms/intergalaktik_ulx5m_gs.py
+180 −0 litex_boards/platforms/lckfb_ljpi.py
+100 −0 litex_boards/platforms/machdyne_kolsch.py
+0 −347 litex_boards/platforms/marble.py
+0 −273 litex_boards/platforms/marblemini.py
+64 −0 litex_boards/platforms/mlkpai_fs01_dr1v90m.py
+279 −0 litex_boards/platforms/myir_myc_j7a100t.py
+21 −0 litex_boards/platforms/olimex_gatemate_a1_evb.py
+313 −0 litex_boards/platforms/puzhi_pz_a7xxt_kfb.py
+234 −0 litex_boards/platforms/qmtech_cyclone10_starterkit.py
+2 −2 litex_boards/platforms/qmtech_xc7k325t.py
+2 −2 litex_boards/platforms/radiona_ulx3s.py
+365 −0 litex_boards/platforms/radiona_ulx4m_ls_v2.py
+333 −0 litex_boards/platforms/sipeed_tang_console.py
+30 −1 litex_boards/platforms/sipeed_tang_nano_20k.py
+9 −4 litex_boards/platforms/sqrl_acorn.py
+354 −0 litex_boards/platforms/xilinx_kcu116.py
+1 −1 litex_boards/platforms/xilinx_zcu106.py
+205 −0 litex_boards/platforms/ypcb_00338_1p1.py
+224 −0 litex_boards/targets/alibaba_vu13p.py
+3 −1 litex_boards/targets/alinx_ax7010.py
+113 −0 litex_boards/targets/alinx_ax7020.py
+172 −0 litex_boards/targets/alinx_ax7203.py
+149 −0 litex_boards/targets/arrow_axe5000.py
+8 −6 litex_boards/targets/berkeleylab_marble.py
+255 −0 litex_boards/targets/berkeleylab_obsidian.py
+80 −0 litex_boards/targets/bochenjingxin_kintex7_basec.py
+66 −5 litex_boards/targets/colognechip_gatemate_evb.py
+2 −2 litex_boards/targets/colorlight_5a_75x.py
+3 −2 litex_boards/targets/digilent_genesys2.py
+30 −0 litex_boards/targets/digilent_nexys_video.py
+12 −3 litex_boards/targets/digilent_zedboard.py
+345 −441 litex_boards/targets/efinix_ti375_c529_dev_kit.py
+6 −0 litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py
+326 −0 litex_boards/targets/efinix_tz170_j484_dev_kit.py
+175 −0 litex_boards/targets/hyvision_pcie_opt01_revf.py
+186 −0 litex_boards/targets/icepi_zero.py
+122 −0 litex_boards/targets/intergalaktik_ulx5m_gs.py
+126 −0 litex_boards/targets/lattice_certuspro_nx_versa.py
+204 −0 litex_boards/targets/lckfb_ljpi.py
+8 −19 litex_boards/targets/litex_acorn_baseboard_mini.py
+171 −0 litex_boards/targets/machdyne_kolsch.py
+78 −0 litex_boards/targets/mlkpai_fs01_dr1v90m.py
+176 −0 litex_boards/targets/myir_myc_j7a100t.py
+58 −2 litex_boards/targets/olimex_gatemate_a1_evb.py
+242 −0 litex_boards/targets/puzhi_pz_a7xxt_kfb.py
+133 −0 litex_boards/targets/qmtech_cyclone10_starterkit.py
+262 −0 litex_boards/targets/radiona_ulx4m_ls_v2.py
+246 −0 litex_boards/targets/sipeed_tang_console.py
+22 −1 litex_boards/targets/sipeed_tang_mega_138k_pro.py
+46 −3 litex_boards/targets/sipeed_tang_nano_20k.py
+0 −0 litex_boards/targets/trenz_te0890.py
+192 −0 litex_boards/targets/xilinx_kcu116.py
+142 −0 litex_boards/targets/ypcb_00338_1p1.py
+1 −1 setup.py
+2 −0 test/test_targets.py
2 changes: 1 addition & 1 deletion third_party/migen