[ImportVerilog] Add delayed assignment support (#9085)

Add the `moore.delayed_assign` and `moore.delayed_nonblocking_assign`
ops to represent `assign #1ns a = b` and `a <= #1ns b` in SystemVerilog,
respectively.

Lower the new delay ops to `llhd.drv` with the appropriate delay value.

Add support for blocking assignments with intra-assignment timing
control to the ImportVerilog conversion. These are pretty trivial, since
the blocking effects of the timing control are simply inserted in
between computing the right-hand side and assigning to the left-hand
side.

Also add support for non-blocking assignments with intra-assignment
delays. These require the new `moore.delayed_nonblocking_assign`, since
the operation cannot suspend execution of the surrounding process.
Instead, the assignment has to be added to the event queue and executed
at a later point in time. Theoretically, the user could type wild things
here, like `a <= repeat(5) @(posedge b or negedge c) d`, which would
require us to spawn a separate "thread" to determine when all the events
have occurred and the assignment can take place. We don't support any of
that for now, because this is just utterly deranged.

Also add support for delayed continuous assignments. This is pretty
trivial since SystemVerilog only allows for simple delay values, such as
`assign #1ns a = b`. This requires the new `moore.delayed_assign` op.

Author: fabianschuiki

include/circt/Dialect/Moore/MooreOps.td

@@ -337,6 +337,16 @@ class AssignOpBase<string mnemonic, list<Trait> traits = []> :
   }];
 }
 
+class DelayedAssignOpBase<string mnemonic, list<Trait> traits = []> :
+    AssignOpBase<mnemonic, traits> {
+  let arguments = (ins RefType:$dst, UnpackedType:$src, TimeType:$delay);
+  let assemblyFormat = [{
+    $dst `,` $src `,` $delay attr-dict `:` type($src)
+  }];
+}
+
+// Continuous assignment
+
 def ContinuousAssignOp : AssignOpBase<"assign", [HasParent<"SVModuleOp">]> {
   let summary = "Continuous assignment within a module";
   let description = [{
@@ -348,6 +358,19 @@ def ContinuousAssignOp : AssignOpBase<"assign", [HasParent<"SVModuleOp">]> {
   }];
 }
 
+def DelayedContinuousAssignOp :
+    DelayedAssignOpBase<"delayed_assign", [HasParent<"SVModuleOp">]> {
+  let summary = "Delayed continuous assignment within a module";
+  let description = [{
+    A continuous assignment with a delay.
+
+    See the `moore.assign` op.
+    See IEEE 1800-2017 § 10.3 "Continuous assignments".
+  }];
+}
+
+// Blocking assignment
+
 def BlockingAssignOp : AssignOpBase<"blocking_assign", [
   DeclareOpInterfaceMethods<PromotableMemOpInterface>
 ]> {
@@ -365,6 +388,8 @@ def BlockingAssignOp : AssignOpBase<"blocking_assign", [
   );
 }
 
+// Non-blocking assignment
+
 def NonBlockingAssignOp : AssignOpBase<"nonblocking_assign"> {
   let summary = "Nonblocking procedural assignment";
   let description = [{
@@ -378,6 +403,17 @@ def NonBlockingAssignOp : AssignOpBase<"nonblocking_assign"> {
   }];
 }
 
+def DelayedNonBlockingAssignOp :
+    DelayedAssignOpBase<"delayed_nonblocking_assign"> {
+  let summary = "Delayed nonblocking procedural assignment";
+  let description = [{
+    A nonblocking procedural assignment with an intra-assignment delay control.
+
+    See the `moore.nonblocking_assign` op.
+    See IEEE 1800-2017 § 9.4.5 "Intra-assignment timing controls".
+  }];
+}
+
 //===----------------------------------------------------------------------===//
 // Statements
 //===----------------------------------------------------------------------===//

lib/Conversion/ImportVerilog/Expressions.cpp

@@ -427,23 +427,46 @@ struct RvalueExprVisitor : public ExprVisitor {
     if (!lhs)
       return {};
 
+    // Determine the right-hand side value of the assignment.
     context.lvalueStack.push_back(lhs);
     auto rhs = context.convertRvalueExpression(
         expr.right(), cast<moore::RefType>(lhs.getType()).getNestedType());
     context.lvalueStack.pop_back();
     if (!rhs)
       return {};
 
+    // If this is a blocking assignment, we can insert the delay/wait ops of the
+    // optional timing control directly in between computing the RHS and
+    // executing the assignment.
+    if (!expr.isNonBlocking()) {
+      if (expr.timingControl)
+        if (failed(context.convertTimingControl(*expr.timingControl)))
+          return {};
+      moore::BlockingAssignOp::create(builder, loc, lhs, rhs);
+      return rhs;
+    }
+
+    // For non-blocking assignments, we only support time delays for now.
     if (expr.timingControl) {
+      // Handle regular time delays.
+      if (auto *ctrl = expr.timingControl->as_if<slang::ast::DelayControl>()) {
+        auto delay = context.convertRvalueExpression(
+            ctrl->expr, moore::TimeType::get(builder.getContext()));
+        if (!delay)
+          return {};
+        moore::DelayedNonBlockingAssignOp::create(builder, loc, lhs, rhs,
+                                                  delay);
+        return rhs;
+      }
+
+      // All other timing controls are not supported.
       auto loc = context.convertLocation(expr.timingControl->sourceRange);
-      mlir::emitError(loc, "delayed assignments not supported");
+      mlir::emitError(loc)
+          << "unsupported non-blocking assignment timing control: "
+          << slang::ast::toString(expr.timingControl->kind);
       return {};
     }
-
-    if (expr.isNonBlocking())
-      moore::NonBlockingAssignOp::create(builder, loc, lhs, rhs);
-    else
-      moore::BlockingAssignOp::create(builder, loc, lhs, rhs);
+    moore::NonBlockingAssignOp::create(builder, loc, lhs, rhs);
     return rhs;
   }
 

lib/Conversion/ImportVerilog/ImportVerilogInternals.h

@@ -134,7 +134,14 @@ struct Context {
                             const slang::ast::Symbol &outermostModule);
   LogicalResult traverseInstanceBody(const slang::ast::Symbol &symbol);
 
-  // Convert a slang timing control into an MLIR timing control.
+  // Convert timing controls into a corresponding set of ops that delay
+  // execution of the current block. Produces an error if the implicit event
+  // control `@*` or `@(*)` is used.
+  LogicalResult convertTimingControl(const slang::ast::TimingControl &ctrl);
+  // Convert timing controls into a corresponding set of ops that delay
+  // execution of the current block. Then converts the given statement, taking
+  // note of the rvalues it reads and adding them to a wait op in case an
+  // implicit event control `@*` or `@(*)` is used.
   LogicalResult convertTimingControl(const slang::ast::TimingControl &ctrl,
                                      const slang::ast::Statement &stmt);
 

lib/Conversion/ImportVerilog/Structure.cpp

@@ -498,12 +498,6 @@ struct ModuleVisitor : public BaseVisitor {
 
   // Handle continuous assignments.
   LogicalResult visit(const slang::ast::ContinuousAssignSymbol &assignNode) {
-    if (const auto *delay = assignNode.getDelay()) {
-      auto loc = context.convertLocation(delay->sourceRange);
-      return mlir::emitError(loc,
-                             "delayed continuous assignments not supported");
-    }
-
     const auto &expr =
         assignNode.getAssignment().as<slang::ast::AssignmentExpression>();
     auto lhs = context.convertLvalueExpression(expr.left());
@@ -515,6 +509,19 @@ struct ModuleVisitor : public BaseVisitor {
     if (!rhs)
       return failure();
 
+    // Handle delayed assignments.
+    if (auto *timingCtrl = assignNode.getDelay()) {
+      auto *ctrl = timingCtrl->as_if<slang::ast::DelayControl>();
+      assert(ctrl && "slang guarantees this to be a simple delay");
+      auto delay = context.convertRvalueExpression(
+          ctrl->expr, moore::TimeType::get(builder.getContext()));
+      if (!delay)
+        return failure();
+      moore::DelayedContinuousAssignOp::create(builder, loc, lhs, rhs, delay);
+      return success();
+    }
+
+    // Otherwise this is a regular assignment.
     moore::ContinuousAssignOp::create(builder, loc, lhs, rhs);
     return success();
   }

lib/Conversion/ImportVerilog/TimingControls.cpp

@@ -155,7 +155,7 @@ struct LTLClockControlVisitor {
 // be handled by `handleDelayControl`.
 static LogicalResult handleRoot(Context &context,
                                 const slang::ast::TimingControl &ctrl,
-                                moore::WaitEventOp &implicitWaitOp) {
+                                moore::WaitEventOp *implicitWaitOp) {
   auto &builder = context.builder;
   auto loc = context.convertLocation(ctrl.sourceRange);
 
@@ -178,7 +178,9 @@ static LogicalResult handleRoot(Context &context,
     // empty wait op and let `Context::convertTimingControl` populate it once
     // the statement has been lowered.
   case TimingControlKind::ImplicitEvent:
-    implicitWaitOp = moore::WaitEventOp::create(builder, loc);
+    if (!implicitWaitOp)
+      return mlir::emitError(loc) << "implicit events cannot be used here";
+    *implicitWaitOp = moore::WaitEventOp::create(builder, loc);
     return success();
 
     // Handle event control.
@@ -206,6 +208,11 @@ static LogicalResult handleRoot(Context &context,
   }
 }
 
+LogicalResult
+Context::convertTimingControl(const slang::ast::TimingControl &ctrl) {
+  return handleRoot(*this, ctrl, nullptr);
+}
+
 LogicalResult
 Context::convertTimingControl(const slang::ast::TimingControl &ctrl,
                               const slang::ast::Statement &stmt) {
@@ -221,7 +228,7 @@ Context::convertTimingControl(const slang::ast::TimingControl &ctrl,
     // surrounding implicit event control's list of implicitly observed
     // variables.
     rvalueReadCallback = nullptr;
-    if (failed(handleRoot(*this, ctrl, implicitWaitOp)))
+    if (failed(handleRoot(*this, ctrl, &implicitWaitOp)))
       return failure();
   }
 

lib/Conversion/MooreToCore/MooreToCore.cpp

@@ -1470,21 +1470,34 @@ struct AssignedVariableOpConversion
   }
 };
 
-template <typename OpTy, unsigned DeltaTime, unsigned EpsilonTime>
+template <typename OpTy>
 struct AssignOpConversion : public OpConversionPattern<OpTy> {
   using OpConversionPattern<OpTy>::OpConversionPattern;
   using OpAdaptor = typename OpTy::Adaptor;
 
   LogicalResult
   matchAndRewrite(OpTy op, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
-    // TODO: When we support delay control in Moore dialect, we need to update
-    // this conversion.
-    auto timeAttr = llhd::TimeAttr::get(
-        op->getContext(), 0U, llvm::StringRef("ns"), DeltaTime, EpsilonTime);
-    auto time = llhd::ConstantTimeOp::create(rewriter, op->getLoc(), timeAttr);
-    rewriter.replaceOpWithNewOp<llhd::DriveOp>(op, adaptor.getDst(),
-                                               adaptor.getSrc(), time, Value{});
+    // Determine the delay for the assignment.
+    Value delay;
+    if constexpr (std::is_same_v<OpTy, ContinuousAssignOp> ||
+                  std::is_same_v<OpTy, BlockingAssignOp>) {
+      // Blocking and continuous assignments get a 0ns 0d 1e delay.
+      delay = llhd::ConstantTimeOp::create(
+          rewriter, op->getLoc(),
+          llhd::TimeAttr::get(op->getContext(), 0U, "ns", 0, 1));
+    } else if constexpr (std::is_same_v<OpTy, NonBlockingAssignOp>) {
+      // Non-blocking assignments get a 0ns 1d 0e delay.
+      delay = llhd::ConstantTimeOp::create(
+          rewriter, op->getLoc(),
+          llhd::TimeAttr::get(op->getContext(), 0U, "ns", 1, 0));
+    } else {
+      // Delayed assignments have a delay operand.
+      delay = adaptor.getDelay();
+    }
+
+    rewriter.replaceOpWithNewOp<llhd::DriveOp>(
+        op, adaptor.getDst(), adaptor.getSrc(), delay, Value{});
     return success();
   }
 };
@@ -1973,9 +1986,11 @@ static void populateOpConversion(ConversionPatternSet &patterns,
     AShrOpConversion,
 
     // Patterns of assignment operations.
-    AssignOpConversion<ContinuousAssignOp, 0, 1>,
-    AssignOpConversion<BlockingAssignOp, 0, 1>,
-    AssignOpConversion<NonBlockingAssignOp, 1, 0>,
+    AssignOpConversion<ContinuousAssignOp>,
+    AssignOpConversion<DelayedContinuousAssignOp>,
+    AssignOpConversion<BlockingAssignOp>,
+    AssignOpConversion<NonBlockingAssignOp>,
+    AssignOpConversion<DelayedNonBlockingAssignOp>,
     AssignedVariableOpConversion,
 
     // Patterns of branch operations.

test/Conversion/ImportVerilog/basic.sv

@@ -3245,3 +3245,66 @@ function automatic void ConcatSformatf(string testStr, string otherString, ref s
    // CHECK-NEXT: moore.blocking_assign [[LV]], [[CONV]] : l64
    $sformat(logicVector, "%s %s", testStr, otherString);
 endfunction
+
+// CHECK-LABEL: moore.module @ContinuousAssignment(
+module ContinuousAssignment;
+  // CHECK-NEXT: [[A:%.+]] = moore.variable
+  // CHECK-NEXT: [[B:%.+]] = moore.variable
+  bit [41:0] a;
+  bit [41:0] b;
+
+  // CHECK-NEXT: [[TMP:%.+]] = moore.read [[B]]
+  // CHECK-NEXT: [[NOTB:%.+]] = moore.not [[TMP]]
+  // CHECK-NEXT: moore.assign [[A]], [[NOTB]]
+  assign a = ~b;
+
+  // CHECK-NEXT: [[TMP:%.+]] = moore.read [[B]]
+  // CHECK-NEXT: [[NOTB:%.+]] = moore.not [[TMP]]
+  // CHECK-NEXT: [[TIME:%.+]] = moore.constant_time 1000000 fs
+  // CHECK-NEXT: moore.delayed_assign [[A]], [[NOTB]], [[TIME]]
+  assign #1ns a = ~b;
+endmodule
+
+// CHECK-LABEL: func.func private @BlockingAssignment(
+// CHECK-SAME: [[A:%.+]]: !moore.ref<i42>
+// CHECK-SAME: [[B:%.+]]: !moore.i42
+// CHECK-SAME: [[C:%.+]]: !moore.i1
+task BlockingAssignment(
+  output bit [41:0] a,
+  input  bit [41:0] b,
+  input  bit c
+);
+  // CHECK-NEXT: [[NOTB:%.+]] = moore.not [[B]]
+  // CHECK-NEXT: moore.blocking_assign [[A]], [[NOTB]]
+  a = ~b;
+
+  // CHECK-NEXT: [[NOTB:%.+]] = moore.not [[B]]
+  // CHECK-NEXT: [[TIME:%.+]] = moore.constant_time 1000000 fs
+  // CHECK-NEXT: moore.wait_delay [[TIME]]
+  // CHECK-NEXT: moore.blocking_assign [[A]], [[NOTB]]
+  a = #1ns ~b;
+
+  // CHECK-NEXT: [[NOTB:%.+]] = moore.not [[B]]
+  // CHECK-NEXT: moore.wait_event {
+  // CHECK-NEXT:   moore.detect_event posedge [[C]]
+  // CHECK-NEXT: }
+  // CHECK-NEXT: moore.blocking_assign [[A]], [[NOTB]]
+  a = @(posedge c) ~b;
+endtask
+
+// CHECK-LABEL: func.func private @NonBlockingAssignment(
+// CHECK-SAME: [[A:%.+]]: !moore.ref<i42>
+// CHECK-SAME: [[B:%.+]]: !moore.i42
+task NonBlockingAssignment(
+  output bit [41:0] a,
+  input  bit [41:0] b
+);
+  // CHECK-NEXT: [[NOTB:%.+]] = moore.not [[B]]
+  // CHECK-NEXT: moore.nonblocking_assign [[A]], [[NOTB]]
+  a <= ~b;
+
+  // CHECK-NEXT: [[NOTB:%.+]] = moore.not [[B]]
+  // CHECK-NEXT: [[TIME:%.+]] = moore.constant_time 1000000 fs
+  // CHECK-NEXT: moore.delayed_nonblocking_assign [[A]], [[NOTB]], [[TIME]]
+  a <= #1ns ~b;
+endtask

test/Conversion/ImportVerilog/errors.sv

@@ -41,15 +41,16 @@ endmodule
 // -----
 module Foo;
   int x;
-  // expected-error @below {{delayed assignments not supported}}
-  initial x <= #1ns x;
+  bit y;
+  // expected-error @below {{unsupported non-blocking assignment timing control: SignalEvent}}
+  initial x <= @y x;
 endmodule
 
 // -----
 module Foo;
   int x;
-  // expected-error @below {{delayed continuous assignments not supported}}
-  assign #1ns x = x;
+  // expected-error @below {{implicit events cannot be used here}}
+  initial x = @* x;
 endmodule
 
 // -----

test/Conversion/MooreToCore/basic.mlir

@@ -1305,3 +1305,28 @@ moore.module @MultiDimensionalSlice(in %in : !moore.array<2 x array<2 x l2>>, ou
   %0 = moore.extract %in from 0 : array<2 x array<2 x l2>> -> array<2 x l2>
   moore.output %0 : !moore.array<2 x l2>
 }
+
+// CHECK-LABEL: hw.module @ContinuousAssignment
+// CHECK-SAME: in %a : !llhd.ref<i42>
+// CHECK-SAME: in %b : i42
+// CHECK-SAME: in %c : !llhd.time
+moore.module @ContinuousAssignment(in %a: !moore.ref<i42>, in %b: !moore.i42, in %c: !moore.time) {
+  // CHECK-NEXT: [[DELTA:%.+]] = llhd.constant_time <0ns, 0d, 1e>
+  // CHECK-NEXT: llhd.drv %a, %b after [[DELTA]]
+  moore.assign %a, %b : i42
+  // CHECK-NEXT: llhd.drv %a, %b after %c
+  moore.delayed_assign %a, %b, %c : i42
+}
+
+// CHECK-LABEL: func.func @NonBlockingAssignment
+// CHECK-SAME: %arg0: !llhd.ref<i42>
+// CHECK-SAME: %arg1: i42
+// CHECK-SAME: %arg2: !llhd.time
+func.func @NonBlockingAssignment(%arg0: !moore.ref<i42>, %arg1: !moore.i42, %arg2: !moore.time) {
+  // CHECK-NEXT: [[DELTA:%.+]] = llhd.constant_time <0ns, 1d, 0e>
+  // CHECK-NEXT: llhd.drv %arg0, %arg1 after [[DELTA]]
+  moore.nonblocking_assign %arg0, %arg1 : i42
+  // CHECK-NEXT: llhd.drv %arg0, %arg1 after %arg2
+  moore.delayed_nonblocking_assign %arg0, %arg1, %arg2 : i42
+  return
+}