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Pull requests: llvm/circt

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174 Open 6,538 Closed
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Pull requests list

[RTG][EmbedValidationValuesPass] Allow ID duplicates if values match RTG Involving the `rtg` dialect
#9061 opened Oct 6, 2025 by maerhart Loading…
1
[RTG] Add isa.space operation RTG Involving the `rtg` dialect
#9060 opened Oct 6, 2025 by maerhart Loading…
1
[RTG] Add VirtualRegisterConfigAttr RTG Involving the `rtg` dialect
#9059 opened Oct 6, 2025 by maerhart Loading…
[circt-verilog-lsp] Minimize project-scope File IO
#9056 opened Oct 6, 2025 by Scheremo Loading…
[CombToSynth] Compute Kogge-Stone prefix tree lazily in unsigned comparison lowering
#9050 opened Oct 4, 2025 by uenoku Loading…
1
No custom printer for CompReg - leading to loss of quotation marks Resolves #8833
#9049 opened Oct 4, 2025 by KaiS987 Loading…
1
Add an attribute to hw.module.extern referencing emit.file ops that implement them
#9047 opened Oct 2, 2025 by tmckay-sifive Loading…
5
[circt-lsp-verilog] "Debounce" onDidChange calls; update in worker
#9046 opened Oct 2, 2025 by Scheremo • Draft
3
fix: corner cases in aggregate generation
#9036 opened Sep 30, 2025 by tianrui-wei Loading…
6
[Synth ] feat : Fold Majority Graph
#9033 opened Sep 27, 2025 by markram1729 • Draft
21
[FIRRTL] Make Domains ClassLike
#9032 opened Sep 27, 2025 by seldridge • Draft
1 task done
8
[LTL] Add explict clocked operations and types
#9026 opened Sep 26, 2025 by Clo91eaf • Draft
8
fix: use NLA to preserve externalized memory from being dropped
#9012 opened Sep 24, 2025 by tianrui-wei Loading…
1
5
[ImportVerilog][Feature] Add debug printer & debug prints
#8992 opened Sep 19, 2025 by Scheremo • Draft
1
[DoNotMerge] Add signal trace capability to arcilator Arc Involving the `arc` dialect
#8986 opened Sep 18, 2025 by fzi-hielscher • Draft
1
[FIRRTL] Add LowerDomains pass FIRRTL Involving the `firrtl` dialect
#8929 opened Sep 5, 2025 by seldridge Loading…
96
[ESI] Unpack dictionary arguments for CallbackPort callbacks
#8916 opened Sep 2, 2025 by mortbopet Loading…
1
[ESI] Throw exceptions on invalid deserialization
#8914 opened Sep 2, 2025 by mortbopet Loading…
3
[ESI] Don't swallow exception in callback port wrapper
#8913 opened Sep 2, 2025 by mortbopet Loading…
3
[Verif] fix : Verif Clock I1 to !seq.clock
#8907 opened Aug 30, 2025 by markram1729 • Draft
[FIRRTL] Add InferDomains pass
#8877 opened Aug 20, 2025 by seldridge • Draft
6
[LLHD] Remove redundant destination operands from wait operation LLHD
#8870 opened Aug 18, 2025 by mvpant • Draft
19
[circt-opt] Add pass --convert-core-to-fsm
#8852 opened Aug 14, 2025 by AtticusKuhn Loading…
20
[SV] Remove extract-test-code
#8846 opened Aug 12, 2025 by rwy7 Loading…
6
Add check for casting bundle with elements in different directions
#8750 opened Jul 21, 2025 by unlsycn Loading…
1
ProTip! What’s not been updated in a month: updated:<2025-09-06.