[FSM] Lower FSM to SMT dialect
#9379
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luisacicolini
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TaoBi22
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Jan 30, 2026
| fsm.transition @S0 | ||
| } | ||
| } | ||
| } No newline at end of file |
| // CHECK-NEXT: } | ||
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| module @fsm_with_time { |
Contributor
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Does this FSM have specific characteristics to make it suitable for the timed test? If not then you could do this in basic.mlir with a --check-prefix (like in
circt/test/arcilator/arcilator.mlir
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| // CHECK-NEXT: %c0_i8 = hw.constant 0 : i8 | ||
| // CHECK-NEXT: %c50_i8 = hw.constant 50 : i8 | ||
| // CHECK-NEXT: %c50_i32 = hw.constant 50 : i32 | ||
| // CHECK-NEXT: %c1_i32 = hw.constant 1 : i32 | ||
| // CHECK-NEXT: %true = hw.constant true | ||
| // CHECK-NEXT: %F_S0 = smt.declare_fun "F_S0" : !smt.func<(!smt.bv<8>, !smt.bv<32>) !smt.bool> | ||
| // CHECK-NEXT: %F_S1 = smt.declare_fun "F_S1" : !smt.func<(!smt.bv<8>, !smt.bv<32>) !smt.bool> |
Contributor
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Could these SSA values be matched as FileCheck variables instead of using raw names? (It's a bit more stable if the naming changes for some reason)
| // Read options from the generated base | ||
| LoweringConfig cfg; | ||
| cfg.withTime = withTime; // default false | ||
| cfg.timeWidth = 5; |
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Worth making this a pass option?
| SmallVector<std::string> &states, Location &loc) { | ||
| std::string nextState = t.getNextState().str(); | ||
| Transition tr = {from, insertStates(states, nextState)}; | ||
| if (!t.getGuard().empty()) { |
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Suggested change
| if (!t.getGuard().empty()) { | |
| if (t.hasGuard()) { |
| } | ||
| } else { | ||
| // Ignore assertions in action regions | ||
| mlir::emitWarning(loc, "Assertions in action regions are ignored."); |
Contributor
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nit:
Suggested change
| mlir::emitWarning(loc, "Assertions in action regions are ignored."); | |
| newOp->emitWarning("Assertions in action regions are ignored."); |
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| if (!isa<verif::AssertOp>(newOp)) { | ||
| // Retrieve the guard value | ||
| if (isa<fsm::ReturnOp>(newOp)) { |
| } else { | ||
| // Ignore assertions in guard regions | ||
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| mlir::emitWarning(loc, "Assertions in guard regions are ignored."); |
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| if (!isa<verif::AssertOp>(newOp)) { | ||
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| // Retrieve all the operands of the output operation | ||
| if (isa<fsm::OutputOp>(newOp)) { |
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| if (!isa<fsm::OutputOp>(op) && !isa<fsm::UpdateOp>(op) && | ||
| !isa<fsm::ReturnOp>(op)) { |
Contributor
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I think you can just do
Suggested change
| if (!isa<fsm::OutputOp>(op) && !isa<fsm::UpdateOp>(op) && | |
| !isa<fsm::ReturnOp>(op)) { | |
| if (!isa<fsm::OutputOp, fsm::UpdateOp, fsm::ReturnOp>(op)) { |
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This PR lowers the FSM dialect into SMT-LIB assertions.
We represent a transition
s0 -> s1as a Constrained Horn Clause (CHC), i.e., as an implication.