[FIRRTL] Remove dead annotations relating to taps and blackboxes. (#9146)

Author: dtzSiFive

include/circt/Dialect/FIRRTL/AnnotationDetails.h

@@ -102,33 +102,12 @@ constexpr const char *augmentedVectorTypeClass =
     "sifive.enterprise.grandcentral.AugmentedVectorType"; // not an annotation
 constexpr const char *dataTapsClass =
     "sifive.enterprise.grandcentral.DataTapsAnnotation";
-constexpr const char *dataTapsBlackboxClass =
-    "sifive.enterprise.grandcentral.DataTapsAnnotation.blackbox"; // not in SFC
 constexpr const char *memTapClass =
     "sifive.enterprise.grandcentral.MemTapAnnotation";
-constexpr const char *memTapBlackboxClass =
-    "sifive.enterprise.grandcentral.MemTapAnnotation.blackbox"; // not in SFC
-constexpr const char *memTapPortClass =
-    "sifive.enterprise.grandcentral.MemTapAnnotation.port"; // not in SFC
-constexpr const char *memTapSourceClass =
-    "sifive.enterprise.grandcentral.MemTapAnnotation.source"; // not in SFC
-constexpr const char *deletedKeyClass =
-    "sifive.enterprise.grandcentral.DeletedDataTapKey";
-constexpr const char *literalKeyClass =
-    "sifive.enterprise.grandcentral.LiteralDataTapKey";
 constexpr const char *referenceKeyClass =
     "sifive.enterprise.grandcentral.ReferenceDataTapKey";
-constexpr const char *referenceKeyPortClass =
-    "sifive.enterprise.grandcentral.ReferenceDataTapKey.port"; // not in SFC
-constexpr const char *referenceKeySourceClass =
-    "sifive.enterprise.grandcentral.ReferenceDataTapKey.source"; // not in SFC
 constexpr const char *internalKeyClass =
     "sifive.enterprise.grandcentral.DataTapModuleSignalKey";
-constexpr const char *internalKeyPortClass =
-    "sifive.enterprise.grandcentral.DataTapModuleSignalKey.port"; // not in SFC
-constexpr const char *internalKeySourceClass =
-    "sifive.enterprise.grandcentral.DataTapModuleSignalKey.source"; // not in
-                                                                    // SFC
 constexpr const char *extractGrandCentralClass =
     "sifive.enterprise.grandcentral.ExtractGrandCentralAnnotation";
 constexpr const char *grandCentralHierarchyFileAnnoClass =

lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp

@@ -836,9 +836,11 @@ CreateSiFiveMetadataPass::emitSitestBlackboxMetadata(ObjectModelIR &omir) {
 
   // Any extmodule with these annotations should be excluded from the blackbox
   // list if it doesn't declare any additional libraries.
-  std::array<StringRef, 6> blackListedAnnos = {
-      blackBoxAnnoClass, blackBoxInlineAnnoClass, blackBoxPathAnnoClass,
-      dataTapsBlackboxClass, memTapBlackboxClass};
+  std::array<StringRef, 3> blackListedAnnos = {
+      blackBoxAnnoClass,
+      blackBoxInlineAnnoClass,
+      blackBoxPathAnnoClass,
+  };
 
   auto *context = &getContext();
 

lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp

@@ -605,18 +605,8 @@ static llvm::StringMap<AnnoRecord> annotationRecords{{
     {augmentedGroundTypeClass, {stdResolve, applyWithoutTarget<true>}},
     // Grand Central Data Tap Annotations
     {dataTapsClass, {noResolve, applyGCTDataTaps}},
-    {dataTapsBlackboxClass, {stdResolve, applyWithoutTarget<true>}},
-    {referenceKeySourceClass, {stdResolve, applyWithoutTarget<true>}},
-    {referenceKeyPortClass, {stdResolve, applyWithoutTarget<true>}},
-    {internalKeySourceClass, {stdResolve, applyWithoutTarget<true>}},
-    {internalKeyPortClass, {stdResolve, applyWithoutTarget<true>}},
-    {deletedKeyClass, {stdResolve, applyWithoutTarget<true>}},
-    {literalKeyClass, {stdResolve, applyWithoutTarget<true>}},
     // Grand Central Mem Tap Annotations
     {memTapClass, {noResolve, applyGCTMemTaps}},
-    {memTapSourceClass, {stdResolve, applyWithoutTarget<true>}},
-    {memTapPortClass, {stdResolve, applyWithoutTarget<true>}},
-    {memTapBlackboxClass, {stdResolve, applyWithoutTarget<true>}},
     // Miscellaneous Annotations
     {conventionAnnoClass, {stdResolve, applyConventionAnno}},
     {typeLoweringAnnoClass, {stdResolve, applyBodyTypeLoweringAnno}},

lib/Dialect/FIRRTL/Transforms/MemToRegOfVec.cpp

@@ -337,35 +337,6 @@ struct MemToRegOfVecPass
     return false;
   }
 
-  void scatterMemTapAnno(RegOp op, ArrayAttr attr,
-                         ImplicitLocOpBuilder &builder) {
-    AnnotationSet annos(attr);
-    SmallVector<Attribute> regAnnotations;
-    auto vecType = type_cast<FVectorType>(op.getResult().getType());
-    for (auto anno : annos) {
-      if (anno.isClass(memTapSourceClass)) {
-        for (size_t i = 0, e = type_cast<FVectorType>(op.getResult().getType())
-                                   .getNumElements();
-             i != e; ++i) {
-          NamedAttrList newAnno;
-          newAnno.append("class", anno.getMember("class"));
-          newAnno.append("circt.fieldID",
-                         builder.getI64IntegerAttr(vecType.getFieldID(i)));
-          newAnno.append("id", anno.getMember("id"));
-          if (auto nla = anno.getMember("circt.nonlocal"))
-            newAnno.append("circt.nonlocal", nla);
-          newAnno.append(
-              "portID",
-              IntegerAttr::get(IntegerType::get(builder.getContext(), 64), i));
-
-          regAnnotations.push_back(builder.getDictionaryAttr(newAnno));
-        }
-      } else
-        regAnnotations.push_back(anno.getAttr());
-    }
-    op.setAnnotationsAttr(builder.getArrayAttr(regAnnotations));
-  }
-
   /// Generate the logic for implementing the memory using Registers.
   void generateMemory(MemOp memOp, FirMemory &firMem) {
     ImplicitLocOpBuilder builder(memOp.getLoc(), memOp);
@@ -404,7 +375,7 @@ struct MemToRegOfVecPass
 
         // Copy all the memory annotations.
         if (!memOp.getAnnotationsAttr().empty())
-          scatterMemTapAnno(regOfVec, memOp.getAnnotationsAttr(), builder);
+          regOfVec.setAnnotationsAttr(memOp.getAnnotationsAttr());
         if (innerSym)
           regOfVec.setInnerSymAttr(memOp.getInnerSymAttr());
       }

test/Dialect/FIRRTL/emit-metadata.mlir

@@ -263,22 +263,6 @@ firrtl.circuit "BasicBlackboxes" attributes {
     ],
     defname = "ignored1"
   }
-  firrtl.extmodule @ignored2() attributes {
-    annotations = [
-      {
-        class = "sifive.enterprise.grandcentral.DataTapsAnnotation.blackbox"
-      }
-    ],
-    defname = "ignored2"
-  }
-  firrtl.extmodule @ignored3() attributes {
-    annotations = [
-      {
-        class = "sifive.enterprise.grandcentral.MemTapAnnotation.blackbox", id = 4 : i64
-      }
-    ],
-    defname = "ignored3"
-  }
   firrtl.extmodule @ignored4() attributes {
     annotations = [
       {

test/Dialect/FIRRTL/mem-to-reg-of-vec.mlir

@@ -194,35 +194,6 @@ firrtl.circuit "WriteMask" attributes {annotations = [
   }
 }
 
-firrtl.circuit "MemTap" attributes {annotations = [
-  {class = "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"}
-]} {
-  firrtl.module public @MemTap() attributes {annotations = [
-    {class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}
-  ]} {
-		%rf_MPORT, %rf_io_rdata_0_MPORT, %rf_io_rdata_1_MPORT = firrtl.mem sym @rf Undefined {
-      annotations = [
-        {class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64}
-      ],
-      depth = 4 : i64,
-      name = "rf",
-      portNames = ["MPORT", "io_rdata_0_MPORT", "io_rdata_1_MPORT"],
-      readLatency = 0 : i32,
-      writeLatency = 1 : i32
-    } : !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data: uint<32>, mask: uint<1>>,
-        !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data flip: uint<32>>,
-        !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data flip: uint<32>>
-    // CHECK-LABEL: firrtl.module public @MemTap()
-    // CHECK:         %rf = firrtl.reg sym @rf %2
-    // CHECK-SAME:      [{circt.fieldID = 1 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 0 : i64}
-    // CHECK-SAME:       {circt.fieldID = 2 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 1 : i64},
-    // CHECK-SAME:       {circt.fieldID = 3 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 2 : i64},
-    // CHECK-SAME:       {circt.fieldID = 4 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 3 : i64}]}
-    // CHECK-SAME:      : !firrtl.clock, !firrtl.vector<uint<32>, 4>
-	}
-
-}
-
 // Test the behavior of non-local annotations using either the old or new
 // format work correctly.
 //