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Kavya Chopra
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added tests for moore2core and sim
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3 files changed

+125
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3 files changed

+125
-4
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‎test/Conversion/MooreToCore/basic.mlir‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -386,7 +386,7 @@ func.func @Statements(%arg0: !moore.i42) {
386386
}
387387

388388
// CHECK-LABEL: func @FormatStrings
389-
func.func @FormatStrings(%arg0: !moore.i42) {
389+
func.func @FormatStrings(%arg0: !moore.i42, %arg1: !moore.f32, %arg2: !moore.f64) {
390390
// CHECK: [[TMP:%.+]] = sim.fmt.literal "hello"
391391
%0 = moore.fmt.literal "hello"
392392
// CHECK: sim.fmt.concat ([[TMP]], [[TMP]])
@@ -411,6 +411,21 @@ func.func @FormatStrings(%arg0: !moore.i42) {
411411
moore.fmt.int hex_lower %arg0, align right, pad zero : i42
412412
// CHECK: sim.fmt.hex %arg0, isUpper true paddingChar 32 specifierWidth 42 : i42
413413
moore.fmt.int hex_upper %arg0, align right, pad space width 42 : i42
414+
415+
// CHECK: sim.fmt.flt %arg1 {isLeftAligned = true} : f32
416+
moore.fmt.real float %arg1, align left : f32
417+
// CHECK: sim.fmt.exp %arg2 {isLeftAligned = true} : f64
418+
moore.fmt.real exponential %arg2, align left : f64
419+
// CHECK: sim.fmt.gen %arg1 {isLeftAligned = true} : f32
420+
moore.fmt.real general %arg1, align left {fracDigits = 6 : i32}: f32
421+
// CHECK: sim.fmt.flt %arg2 {fracDigits = 10 : i32, isLeftAligned = true} : f64
422+
moore.fmt.real float %arg2, align left {fracDigits = 10 : i32}: f64
423+
// CHECK: sim.fmt.exp %arg1 {fieldWidth = 9 : i32, fracDigits = 8 : i32} : f32
424+
moore.fmt.real exponential %arg1, align right {fieldWidth = 9 : i32, fracDigits = 8 : i32}: f32
425+
// CHECK: sim.fmt.gen %arg2 : f64
426+
moore.fmt.real general %arg2, align right : f64
427+
// CHECK: sim.fmt.flt %arg1 {fieldWidth = 15 : i32} : f32
428+
moore.fmt.real float %arg1, align right {fieldWidth = 15 : i32}: f32
414429
// CHECK: sim.proc.print [[TMP]]
415430
moore.builtin.display %0
416431
return

‎test/Dialect/Sim/format-strings.mlir‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,77 @@ hw.module @constant_fold5(out res: !sim.fstring) {
192192
hw.output %cat : !sim.fstring
193193
}
194194

195+
// CHECK-LABEL: hw.module @constant_fold_real_formats
196+
// CHECK: sim.fmt.literal "5.0e-01 ,0.500000, 0.5;1.6e+00, 1.6,2;9.999990e+05,999999.000000,999999;1.000000e+126,999999999999999924867761618992882042544670869834838461439225972225294199975793026603163493762817653751530058413655532282839040.000000,1e+126"
197+
hw.module @constant_fold_real_formats(out res: !sim.fstring) {
198+
%comma = sim.fmt.literal ","
199+
%semicolon = sim.fmt.literal ";"
200+
%cst_05 = arith.constant 5.000000e-01 : f64
201+
%e0 = sim.fmt.exp %cst_05 {fieldWidth = 20 : i32, fracDigits = 1 : i32, isLeftAligned = true} : f64
202+
%f0 = sim.fmt.flt %cst_05 : f64
203+
%g0 = sim.fmt.gen %cst_05 {fieldWidth = 10 : i32, fracDigits = 9 : i32} : f64
204+
%cst_05_comma = sim.fmt.concat(%e0, %comma, %f0, %comma, %g0)
205+
%cst_165 = arith.constant 1.650000e+00 : f64
206+
%e1 = sim.fmt.exp %cst_165 {fracDigits = 1 : i32} : f64
207+
%f1 = sim.fmt.flt %cst_165 {fieldWidth = 30 : i32, fracDigits = 1 : i32} : f64
208+
%g1 = sim.fmt.gen %cst_165 {fracDigits = 1 : i32} : f64
209+
%cst_165_comma = sim.fmt.concat(%e1, %comma, %f1, %comma, %g1)
210+
%cst_999999 = arith.constant 9.999990e+05 : f64
211+
%e2 = sim.fmt.exp %cst_999999 : f64
212+
%f2 = sim.fmt.flt %cst_999999 : f64
213+
%g2 = sim.fmt.gen %cst_999999 : f64
214+
%cst_999999_comma = sim.fmt.concat(%e2, %comma, %f2, %comma, %g2)
215+
%cst_big = arith.constant 1.000000e+126 : f64
216+
%e3 = sim.fmt.exp %cst_big : f64
217+
%f3 = sim.fmt.flt %cst_big : f64
218+
%g3 = sim.fmt.gen %cst_big : f64
219+
%cst_big_comma = sim.fmt.concat(%e3, %comma, %f3, %comma, %g3)
220+
%res = sim.fmt.concat(%cst_05_comma, %semicolon, %cst_165_comma, %semicolon, %cst_999999_comma, %semicolon, %cst_big_comma)
221+
hw.output %res : !sim.fstring
222+
}
223+
224+
// CHECK-LABEL: hw.module @constant_fold_real_gen_precision
225+
// CHECK: sim.fmt.literal "0.001,0.001,0.0012,0.00123,0.001235,0.001235,0.001235,0.001235;1e-07,1e-07,1.2e-07,1.23e-07,1.235e-07,1.235e-07,1.235e-07,1.235e-07;1e+06,1e+06,1.2e+06,1.24e+06,1.235e+06,1.235e+06,1.235e+06,1235000"
226+
hw.module @constant_fold_real_gen_precision(out res : !sim.fstring) {
227+
%comma = sim.fmt.literal ","
228+
%semicolon = sim.fmt.literal ";"
229+
%cst_a = arith.constant 1.235000e-03 : f64
230+
%a0 = sim.fmt.gen %cst_a {fracDigits = 0 : i32} : f64
231+
%a1 = sim.fmt.gen %cst_a {fracDigits = 1 : i32} : f64
232+
%a2 = sim.fmt.gen %cst_a {fracDigits = 2 : i32} : f64
233+
%a3 = sim.fmt.gen %cst_a {fracDigits = 3 : i32} : f64
234+
%a4 = sim.fmt.gen %cst_a {fracDigits = 4 : i32} : f64
235+
%a5 = sim.fmt.gen %cst_a {fracDigits = 5 : i32} : f64
236+
%a6 = sim.fmt.gen %cst_a {fracDigits = 6 : i32} : f64
237+
%a7 = sim.fmt.gen %cst_a {fracDigits = 7 : i32} : f64
238+
%grp_a = sim.fmt.concat(%a0, %comma, %a1, %comma, %a2, %comma, %a3, %comma, %a4, %comma, %a5, %comma, %a6, %comma, %a7)
239+
240+
%cst_b = arith.constant 1.235000e-07 : f64
241+
%b0 = sim.fmt.gen %cst_b {fracDigits = 0 : i32} : f64
242+
%b1 = sim.fmt.gen %cst_b {fracDigits = 1 : i32} : f64
243+
%b2 = sim.fmt.gen %cst_b {fracDigits = 2 : i32} : f64
244+
%b3 = sim.fmt.gen %cst_b {fracDigits = 3 : i32} : f64
245+
%b4 = sim.fmt.gen %cst_b {fracDigits = 4 : i32} : f64
246+
%b5 = sim.fmt.gen %cst_b {fracDigits = 5 : i32} : f64
247+
%b6 = sim.fmt.gen %cst_b {fracDigits = 6 : i32} : f64
248+
%b7 = sim.fmt.gen %cst_b {fracDigits = 7 : i32} : f64
249+
%grp_b = sim.fmt.concat(%b0, %comma, %b1, %comma, %b2, %comma, %b3, %comma, %b4, %comma, %b5, %comma, %b6, %comma, %b7)
250+
251+
%cst_c = arith.constant 1.235000e+06 : f64
252+
%c0 = sim.fmt.gen %cst_c {fracDigits = 0 : i32} : f64
253+
%c1 = sim.fmt.gen %cst_c {fracDigits = 1 : i32} : f64
254+
%c2 = sim.fmt.gen %cst_c {fracDigits = 2 : i32} : f64
255+
%c3 = sim.fmt.gen %cst_c {fracDigits = 3 : i32} : f64
256+
%c4 = sim.fmt.gen %cst_c {fracDigits = 4 : i32} : f64
257+
%c5 = sim.fmt.gen %cst_c {fracDigits = 5 : i32} : f64
258+
%c6 = sim.fmt.gen %cst_c {fracDigits = 6 : i32} : f64
259+
%c7 = sim.fmt.gen %cst_c {fracDigits = 7 : i32} : f64
260+
%grp_c = sim.fmt.concat(%c0, %comma, %c1, %comma, %c2, %comma, %c3, %comma, %c4, %comma, %c5, %comma, %c6, %comma, %c7)
261+
262+
%res = sim.fmt.concat(%grp_a, %semicolon, %grp_b, %semicolon, %grp_c)
263+
hw.output %res : !sim.fstring
264+
}
265+
195266
// CHECK-LABEL: hw.module @flatten_concat1
196267
// CHECK-DAG: %[[LHL:.+]] = sim.fmt.literal "HexLower: "
197268
// CHECK-DAG: %[[LHU:.+]] = sim.fmt.literal "HexUpper: "

‎test/Dialect/Sim/proceduralize-sim.mlir‎

Lines changed: 38 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,36 @@ hw.module @basic_print3(in %clk : !seq.clock, in %val: i32) {
7878
sim.print %str on %clk if %true
7979
}
8080

81+
// CHECK-LABEL: @basic_real_print
82+
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
83+
// CHECK-NEXT: hw.triggered posedge %[[TRG]](%val) : f64 {
84+
// CHECK-NEXT: ^bb0(%[[ARG:.*]]: f64):
85+
// CHECK-DAG: %[[L1:.*]] = sim.fmt.literal "F: "
86+
// CHECK-DAG: %[[L2:.*]] = sim.fmt.literal ", E: "
87+
// CHECK-DAG: %[[L3:.*]] = sim.fmt.literal ", G: "
88+
// CHECK-DAG: %[[F:.*]] = sim.fmt.flt %[[ARG]] {fracDigits = 2 : i32} : f64
89+
// CHECK-DAG: %[[E:.*]] = sim.fmt.exp %[[ARG]] {fracDigits = 1 : i32} : f64
90+
// CHECK-DAG: %[[G:.*]] = sim.fmt.gen %[[ARG]] {fracDigits = 3 : i32} : f64
91+
// CHECK-DAG: %[[CAT:.*]] = sim.fmt.concat (%[[L1]], %[[F]], %[[L2]], %[[E]], %[[L3]], %[[G]])
92+
// CHECK: sim.proc.print %[[CAT]]
93+
// CHECK-NEXT: }
94+
95+
hw.module @basic_real_print(in %clk : !seq.clock, in %val : f64) {
96+
%true = hw.constant true
97+
98+
%lf = sim.fmt.literal "F: "
99+
%le = sim.fmt.literal ", E: "
100+
%lg = sim.fmt.literal ", G: "
101+
102+
%f = sim.fmt.flt %val {fracDigits = 2 : i32} : f64
103+
%e = sim.fmt.exp %val {fracDigits = 1 : i32} : f64
104+
%g = sim.fmt.gen %val {fracDigits = 3 : i32} : f64
105+
106+
%cat = sim.fmt.concat (%lf, %f, %le, %e, %lg, %g)
107+
sim.print %cat on %clk if %true
108+
}
109+
110+
81111
// CHECK-LABEL: @multi_args
82112
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
83113
// CHECK-NEXT: hw.triggered posedge %0(%a, %b, %c) : i8, i8, i8 {
@@ -167,15 +197,16 @@ hw.module @multi_clock(in %clka : !seq.clock, in %clkb : !seq.clock, in %clkc :
167197

168198
// CHECK-LABEL: @sequence
169199
// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
170-
// CHECK-NEXT: hw.triggered posedge %[[TRG]](%conda, %condb, %val) : i1, i1, i32 {
171-
// CHECK-NEXT: ^bb0(%[[ARG0:.*]]: i1, %[[ARG1:.*]]: i1, %[[ARG2:.*]]: i32):
200+
// CHECK-NEXT: hw.triggered posedge %[[TRG]](%conda, %condb, %val, %rval) : i1, i1, i32, f64 {
201+
// CHECK-NEXT: ^bb0(%[[ARG0:.*]]: i1, %[[ARG1:.*]]: i1, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: f64):
172202
// CHECK-DAG: %[[L1:.*]] = sim.fmt.literal "#1"
173203
// CHECK-DAG: %[[L2:.*]] = sim.fmt.literal "#2"
174204
// CHECK-DAG: %[[L3:.*]] = sim.fmt.literal "#3"
175205
// CHECK-DAG: %[[L4:.*]] = sim.fmt.literal "#4"
176206
// CHECK-DAG: %[[L5:.*]] = sim.fmt.literal "#5"
177207
// CHECK-DAG: %[[L6:.*]] = sim.fmt.literal "#6"
178208
// CHECK-DAG: %[[BIN:.*]] = sim.fmt.bin %[[ARG2]] specifierWidth 32 : i32
209+
// CHECK-DAG: %[[REALFMT:.*]] = sim.fmt.gen %[[ARG3]] {fracDigits = 3 : i32} : f64
179210
// CHECK: scf.if %[[ARG0]] {
180211
// CHECK-NEXT: sim.proc.print %[[L1]]
181212
// CHECK-NEXT: }
@@ -190,10 +221,12 @@ hw.module @multi_clock(in %clka : !seq.clock, in %clkb : !seq.clock, in %clkc :
190221
// CHECK-NEXT: sim.proc.print %[[BIN]]
191222
// CHECK-NEXT: scf.if %[[ARG0]] {
192223
// CHECK-NEXT: sim.proc.print %[[L6]]
224+
// CHECK-NEXT: sim.proc.print %[[REALFMT]]
193225
// CHECK-NEXT: }
194226
// CHECK-NEXT: }
195227

196-
hw.module @sequence(in %clk: !seq.clock, in %conda: i1, in %condb: i1, in %val : i32) {
228+
229+
hw.module @sequence(in %clk: !seq.clock, in %conda: i1, in %condb: i1, in %val : i32, in %rval : f64) {
197230
%true = hw.constant true
198231
%false = hw.constant false
199232

@@ -213,6 +246,8 @@ hw.module @sequence(in %clk: !seq.clock, in %conda: i1, in %condb: i1, in %val :
213246
sim.print %cen on %clk if %true
214247
%6 = sim.fmt.literal "#6"
215248
sim.print %6 on %clk if %conda
249+
%rfmt = sim.fmt.gen %rval {fracDigits = 3 : i32} : f64
250+
sim.print %rfmt on %clk if %conda
216251
}
217252

218253
// CHECK-LABEL: @condition_as_val

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