[circt-verilog] Running SROA on core dialects causes logical mismatches

[fabianschuiki]

I have noticed that enabling the SROA pass in circt-verilog causes logical equivalence checkers to report mismatches when round-tripping Verilog through CIRCT. I'll comment that pass out again since it is not strictly necessary, but it would be good to figure out what's going on there.