[FIRRTL] Domain Inference U-turn Issue

[seldridge]

Consider the following domain inference problem:

FIRRTL version 6.0.0

circuit Foo:

  domain ClockDomain:

  module Bar:
    output a: UInt<1>

    wire b : UInt<1>
    connect a, b

  module Baz:
    input a: UInt<1>

  public module Foo:

    inst bar of Bar
    inst baz of Baz

    connect baz.a, bar.a

With the current domain inference pass in #9106, this presently fails with the following error:

Foo.fir:18:5: error: unable to infer value for undriven domain port "ClockDomain"
    inst bar of Bar
    ^
Foo.fir:18:5: note: associated with hardware port "a"