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[RISCV] Change input register type for QC_SWM and QC_SWMI #70829

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[RISCV] Change input register type for QC_SWM and QC_SWMI

[RISCV] Change input register type for QC_SWM and QC_SWMI #70829

Triggered via pull request June 16, 2025 05:21
@svs-quicsvs-quic
opened #144294
svs-quic:swmreg
Status Success
Total duration 1h 14m 2s
Artifacts 2

premerge.yaml

on: pull_request
Build and Test Linux
32m 37s
Build and Test Linux
Build and Test Windows
1h 10m
Build and Test Windows
MacOS Premerge Checks
0s
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2 warnings
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Cache not found for keys: ccache-
Build and Test Windows
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Artifacts

Produced during runtime
Name Size Digest
Premerge Artifacts (Linux) Expired
1.53 MB
sha256:329e68a19ccc8d3d9b49b1ba42aefdd7f77c6e55e9d17195c0f7a7463ce0a0d6
Premerge Artifacts (Windows) Expired
1.32 MB
sha256:181f1996baea8f6e5a33f73e5e6e16e1f1cdcdf56f1a9a64bfe1632ae8a546b6