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[RISCV] Factor out common SiFive7 scheduling model into an abstraction layer #71350

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[RISCV] Factor out common SiFive7 scheduling model into an abstraction layer

[RISCV] Factor out common SiFive7 scheduling model into an abstraction layer #71350

Triggered via pull request June 16, 2025 22:00
@mshockwavemshockwave
opened #144442
mshockwave:patch/rvv/sifive7-sched-model
Status Success
Total duration 1h 23m 5s
Artifacts 2

premerge.yaml

on: pull_request
Build and Test Linux
34m 1s
Build and Test Linux
Build and Test Windows
1h 15m
Build and Test Windows
MacOS Premerge Checks
0s
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Build and Test Linux
Cache not found for keys: ccache-
Build and Test Windows
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Artifacts

Produced during runtime
Name Size Digest
Premerge Artifacts (Linux) Expired
1.54 MB
sha256:b3cf194d793b06382907156572dd1bb7efed73d66429eb48a7970346580d5dcc
Premerge Artifacts (Windows) Expired
1.33 MB
sha256:79bb3c03508536882d8131c0bc0d3f9d025ebb758cb813fb4a92c5624f367ce7