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harrisonGPUharrisonGPU
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[DAG] Update lit test.
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‎llvm/test/CodeGen/AMDGPU/freeze-binary.ll‎

Lines changed: 126 additions & 138 deletions
Original file line numberDiff line numberDiff line change
@@ -1,221 +1,209 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s
33

44
define float @freeze_fneg(float %input) nounwind {
5-
; GFX11-LABEL: freeze_fneg:
6-
; GFX11: ; %bb.0: ; %entry
7-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8-
; GFX11-NEXT: s_setpc_b64 s[30:31]
9-
entry:
5+
; CHECK-LABEL: freeze_fneg:
6+
; CHECK: ; %bb.0:
7+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8+
; CHECK-NEXT: s_setpc_b64 s[30:31]
109
%x = fneg reassoc nsz arcp contract afn float %input
1110
%y = freeze float %x
1211
%z = fneg reassoc nsz arcp contract afn float %y
1312
ret float %z
1413
}
1514

1615
define <8 x float> @freeze_fneg_vec(<8 x float> %input) nounwind {
17-
; GFX11-LABEL: freeze_fneg_vec:
18-
; GFX11: ; %bb.0: ; %entry
19-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20-
; GFX11-NEXT: s_setpc_b64 s[30:31]
21-
entry:
16+
; CHECK-LABEL: freeze_fneg_vec:
17+
; CHECK: ; %bb.0:
18+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19+
; CHECK-NEXT: s_setpc_b64 s[30:31]
2220
%x = fneg <8 x float> %input
2321
%y = freeze <8 x float> %x
2422
%z = fneg <8 x float> %y
2523
ret <8 x float> %z
2624
}
2725

2826
define float @freeze_fadd(float %input) nounwind {
29-
; GFX11-LABEL: freeze_fadd:
30-
; GFX11: ; %bb.0: ; %entry
31-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
32-
; GFX11-NEXT: v_add_f32_e32 v0, 2.0, v0
33-
; GFX11-NEXT: s_setpc_b64 s[30:31]
34-
entry:
27+
; CHECK-LABEL: freeze_fadd:
28+
; CHECK: ; %bb.0:
29+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
30+
; CHECK-NEXT: v_add_f32_e32 v0, 2.0, v0
31+
; CHECK-NEXT: s_setpc_b64 s[30:31]
3532
%x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
3633
%y = freeze float %x
3734
%z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
3835
ret float %z
3936
}
4037

4138
define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {
42-
; GFX11-LABEL: freeze_fadd_vec:
43-
; GFX11: ; %bb.0: ; %entry
44-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45-
; GFX11-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
46-
; GFX11-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
47-
; GFX11-NEXT: s_setpc_b64 s[30:31]
48-
entry:
39+
; CHECK-LABEL: freeze_fadd_vec:
40+
; CHECK: ; %bb.0:
41+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
42+
; CHECK-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
43+
; CHECK-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
44+
; CHECK-NEXT: s_setpc_b64 s[30:31]
4945
%x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
5046
%y = freeze <4 x float> %x
5147
%z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
5248
ret <4 x float> %z
5349
}
5450

5551
define float @freeze_fsub(float %input) nounwind {
56-
; GFX11-LABEL: freeze_fsub:
57-
; GFX11: ; %bb.0: ; %entry
58-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
59-
; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
60-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
61-
; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
62-
; GFX11-NEXT: s_setpc_b64 s[30:31]
63-
entry:
52+
; CHECK-LABEL: freeze_fsub:
53+
; CHECK: ; %bb.0:
54+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
55+
; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
56+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
57+
; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
58+
; CHECK-NEXT: s_setpc_b64 s[30:31]
6459
%x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+00
6560
%y = freeze float %x
6661
%z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+00
6762
ret float %z
6863
}
6964

7065
define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
71-
; GFX11-LABEL: freeze_fsub_vec:
72-
; GFX11: ; %bb.0: ; %entry
73-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
74-
; GFX11-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
75-
; GFX11-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
76-
; GFX11-NEXT: s_setpc_b64 s[30:31]
77-
entry:
66+
; CHECK-LABEL: freeze_fsub_vec:
67+
; CHECK: ; %bb.0:
68+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69+
; CHECK-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
70+
; CHECK-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
71+
; CHECK-NEXT: s_setpc_b64 s[30:31]
7872
%x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
7973
%y = freeze <4 x float> %x
8074
%z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
8175
ret <4 x float> %z
8276
}
8377

8478
define float @freeze_fmul(float %input) nounwind {
85-
; GFX11-LABEL: freeze_fmul:
86-
; GFX11: ; %bb.0: ; %entry
87-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
88-
; GFX11-NEXT: v_mul_f32_e32 v0, 4.0, v0
89-
; GFX11-NEXT: s_setpc_b64 s[30:31]
90-
entry:
79+
; CHECK-LABEL: freeze_fmul:
80+
; CHECK: ; %bb.0:
81+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
82+
; CHECK-NEXT: v_mul_f32_e32 v0, 4.0, v0
83+
; CHECK-NEXT: s_setpc_b64 s[30:31]
9184
%x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+00
9285
%y = freeze float %x
9386
%z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+00
9487
ret float %z
9588
}
9689

9790
define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
98-
; GFX11-LABEL: freeze_fmul_vec:
99-
; GFX11: ; %bb.0: ; %entry
100-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
101-
; GFX11-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
102-
; GFX11-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
103-
; GFX11-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
104-
; GFX11-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
105-
; GFX11-NEXT: s_setpc_b64 s[30:31]
106-
entry:
91+
; CHECK-LABEL: freeze_fmul_vec:
92+
; CHECK: ; %bb.0:
93+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
94+
; CHECK-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
95+
; CHECK-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
96+
; CHECK-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
97+
; CHECK-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
98+
; CHECK-NEXT: s_setpc_b64 s[30:31]
10799
%x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
108100
%y = freeze <8 x float> %x
109101
%z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
110102
ret <8 x float> %z
111103
}
112104

113105
define float @freeze_fdiv(float %input) nounwind {
114-
; GFX11-LABEL: freeze_fdiv:
115-
; GFX11: ; %bb.0: ; %entry
116-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
117-
; GFX11-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
118-
; GFX11-NEXT: s_setpc_b64 s[30:31]
119-
entry:
106+
; CHECK-LABEL: freeze_fdiv:
107+
; CHECK: ; %bb.0:
108+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
109+
; CHECK-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
110+
; CHECK-NEXT: s_setpc_b64 s[30:31]
120111
%x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00
121112
%y = freeze float %x
122113
%z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00
123114
ret float %z
124115
}
125116

126117
define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
127-
; GFX11-LABEL: freeze_fdiv_vec:
128-
; GFX11: ; %bb.0: ; %entry
129-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
130-
; GFX11-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
131-
; GFX11-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
132-
; GFX11-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
133-
; GFX11-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
134-
; GFX11-NEXT: s_setpc_b64 s[30:31]
135-
entry:
118+
; CHECK-LABEL: freeze_fdiv_vec:
119+
; CHECK: ; %bb.0:
120+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
121+
; CHECK-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
122+
; CHECK-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
123+
; CHECK-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
124+
; CHECK-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
125+
; CHECK-NEXT: s_setpc_b64 s[30:31]
136126
%x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
137127
%y = freeze <8 x float> %x
138128
%z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
139129
ret <8 x float> %z
140130
}
141131

142132
define float @freeze_frem(float %input) nounwind {
143-
; GFX11-LABEL: freeze_frem:
144-
; GFX11: ; %bb.0: ; %entry
145-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
146-
; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
147-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
148-
; GFX11-NEXT: v_trunc_f32_e32 v1, v1
149-
; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
150-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
151-
; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
152-
; GFX11-NEXT: v_trunc_f32_e32 v1, v1
153-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
154-
; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
155-
; GFX11-NEXT: s_setpc_b64 s[30:31]
156-
entry:
133+
; CHECK-LABEL: freeze_frem:
134+
; CHECK: ; %bb.0:
135+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
136+
; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
137+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
138+
; CHECK-NEXT: v_trunc_f32_e32 v1, v1
139+
; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
140+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
141+
; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
142+
; CHECK-NEXT: v_trunc_f32_e32 v1, v1
143+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
144+
; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
145+
; CHECK-NEXT: s_setpc_b64 s[30:31]
157146
%x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00
158147
%y = freeze float %x
159148
%z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00
160149
ret float %z
161150
}
162151

163152
define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
164-
; GFX11-LABEL: freeze_frem_vec:
165-
; GFX11: ; %bb.0: ; %entry
166-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
167-
; GFX11-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
168-
; GFX11-NEXT: v_trunc_f32_e32 v11, v0
169-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
170-
; GFX11-NEXT: v_trunc_f32_e32 v8, v8
171-
; GFX11-NEXT: v_trunc_f32_e32 v9, v9
172-
; GFX11-NEXT: v_mul_f32_e32 v10, 0.5, v6
173-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
174-
; GFX11-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
175-
; GFX11-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
176-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
177-
; GFX11-NEXT: v_trunc_f32_e32 v10, v10
178-
; GFX11-NEXT: v_trunc_f32_e32 v9, v7
179-
; GFX11-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
180-
; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v1
181-
; GFX11-NEXT: v_trunc_f32_e32 v9, v11
182-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
183-
; GFX11-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
184-
; GFX11-NEXT: v_trunc_f32_e32 v8, v8
185-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
186-
; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v8
187-
; GFX11-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
188-
; GFX11-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
189-
; GFX11-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
190-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
191-
; GFX11-NEXT: v_trunc_f32_e32 v8, v10
192-
; GFX11-NEXT: v_trunc_f32_e32 v10, v12
193-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
194-
; GFX11-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
195-
; GFX11-NEXT: v_trunc_f32_e32 v8, v11
196-
; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
197-
; GFX11-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
198-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
199-
; GFX11-NEXT: v_fmac_f32_e32 v7, -4.0, v8
200-
; GFX11-NEXT: v_trunc_f32_e32 v9, v12
201-
; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
202-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
203-
; GFX11-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
204-
; GFX11-NEXT: v_trunc_f32_e32 v9, v11
205-
; GFX11-NEXT: v_trunc_f32_e32 v11, v3
206-
; GFX11-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
207-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
208-
; GFX11-NEXT: v_sub_f32_e32 v3, v3, v11
209-
; GFX11-NEXT: v_trunc_f32_e32 v8, v10
210-
; GFX11-NEXT: v_trunc_f32_e32 v10, v12
211-
; GFX11-NEXT: v_trunc_f32_e32 v12, v4
212-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
213-
; GFX11-NEXT: v_fmac_f32_e32 v2, -2.0, v8
214-
; GFX11-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
215-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
216-
; GFX11-NEXT: v_sub_f32_e32 v4, v4, v12
217-
; GFX11-NEXT: s_setpc_b64 s[30:31]
218-
entry:
153+
; CHECK-LABEL: freeze_frem_vec:
154+
; CHECK: ; %bb.0:
155+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
156+
; CHECK-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
157+
; CHECK-NEXT: v_trunc_f32_e32 v11, v0
158+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
159+
; CHECK-NEXT: v_trunc_f32_e32 v8, v8
160+
; CHECK-NEXT: v_trunc_f32_e32 v9, v9
161+
; CHECK-NEXT: v_mul_f32_e32 v10, 0.5, v6
162+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
163+
; CHECK-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
164+
; CHECK-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
165+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
166+
; CHECK-NEXT: v_trunc_f32_e32 v10, v10
167+
; CHECK-NEXT: v_trunc_f32_e32 v9, v7
168+
; CHECK-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
169+
; CHECK-NEXT: v_mul_f32_e32 v8, 0.5, v1
170+
; CHECK-NEXT: v_trunc_f32_e32 v9, v11
171+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
172+
; CHECK-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
173+
; CHECK-NEXT: v_trunc_f32_e32 v8, v8
174+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
175+
; CHECK-NEXT: v_fmac_f32_e32 v1, -2.0, v8
176+
; CHECK-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
177+
; CHECK-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
178+
; CHECK-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
179+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
180+
; CHECK-NEXT: v_trunc_f32_e32 v8, v10
181+
; CHECK-NEXT: v_trunc_f32_e32 v10, v12
182+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
183+
; CHECK-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
184+
; CHECK-NEXT: v_trunc_f32_e32 v8, v11
185+
; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
186+
; CHECK-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
187+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
188+
; CHECK-NEXT: v_fmac_f32_e32 v7, -4.0, v8
189+
; CHECK-NEXT: v_trunc_f32_e32 v9, v12
190+
; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
191+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
192+
; CHECK-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
193+
; CHECK-NEXT: v_trunc_f32_e32 v9, v11
194+
; CHECK-NEXT: v_trunc_f32_e32 v11, v3
195+
; CHECK-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
196+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
197+
; CHECK-NEXT: v_sub_f32_e32 v3, v3, v11
198+
; CHECK-NEXT: v_trunc_f32_e32 v8, v10
199+
; CHECK-NEXT: v_trunc_f32_e32 v10, v12
200+
; CHECK-NEXT: v_trunc_f32_e32 v12, v4
201+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
202+
; CHECK-NEXT: v_fmac_f32_e32 v2, -2.0, v8
203+
; CHECK-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
204+
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3)
205+
; CHECK-NEXT: v_sub_f32_e32 v4, v4, v12
206+
; CHECK-NEXT: s_setpc_b64 s[30:31]
219207
%x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
220208
%y = freeze <8 x float> %x
221209
%z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>

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