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1 parent 3f10cb4 commit 02d554cCopy full SHA for 02d554c
llvm/lib/Target/X86/X86ScheduleZnver4.td
@@ -667,8 +667,8 @@ def Zn4WriteCMPXCHG8B : SchedWriteRes<[Zn4ALU0123]> {
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def : InstRW<[Zn4WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
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def Zn4WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn4ALU0123]> {
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- let Latency = 4; // FIXME: not from llvm-exegesis
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- let ReleaseAtCycles = [59];
+ let Latency = 2; // FIXME: not from llvm-exegesis
+ let ReleaseAtCycles = [40];
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let NumMicroOps = 26;
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}
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def : InstRW<[Zn4WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
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