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VPERMD uops
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llvm/lib/Target/X86/X86ScheduleZnver4.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1408,8 +1408,8 @@ def : InstRW<[Zn4WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
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def Zn4WriteVPERMPDYmi : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
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let Latency = !add(Znver4Model.VecLoadLatency, Zn4WriteVPERMYri.Latency);
1411-
let ReleaseAtCycles = [1, 1, 2];
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let NumMicroOps = !add(Zn4WriteVPERMYri.NumMicroOps, 1);
1411+
let ReleaseAtCycles = [1, 1, 1];
1412+
let NumMicroOps = 1;
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}
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def : InstRW<[Zn4WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
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@@ -1422,8 +1422,8 @@ def : InstRW<[Zn4WriteVPERMDYrr], (instrs VPERMDYrr)>;
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def Zn4WriteVPERMYm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
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let Latency = !add(Znver4Model.VecLoadLatency, Zn4WriteVPERMDYrr.Latency);
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let ReleaseAtCycles = [1, 1, 2];
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let NumMicroOps = !add(Zn4WriteVPERMDYrr.NumMicroOps, 0);
1425+
let ReleaseAtCycles = [1, 1, 1];
1426+
let NumMicroOps = 1;
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}
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def : InstRW<[Zn4WriteVPERMYm], (instrs VPERMQYmi, VPERMDYrm)>;
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