Skip to content

Commit 06d9ce2

Browse files
committed
Adjust branch/mul/div units
1 parent 9a2658d commit 06d9ce2

File tree

4 files changed

+414
-408
lines changed

4 files changed

+414
-408
lines changed

llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td

Lines changed: 34 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
// We assume that:
1111
// * 6-issue out-of-order CPU with 192 ROB entries.
1212
// * Units:
13-
// * IXU (Integer ALU Unit): 4 units, only one can execute division.
13+
// * IXU (Integer ALU Unit): 4 units, only one can execute mul/div.
1414
// * FXU (Floating-point Unit): 2 units.
1515
// * LSU (Load/Store Unit): 2 units.
1616
// * VXU (Vector Unit): 1 unit.
@@ -39,20 +39,24 @@ let SchedModel = GenericOOOModel in {
3939
//===----------------------------------------------------------------------===//
4040
// Resource groups
4141
//===----------------------------------------------------------------------===//
42-
def GenericOOODIV : ProcResource<1>;
43-
def GenericOOOIXU : ProcResource<3>;
44-
def GenericOOOALU : ProcResGroup<[GenericOOODIV, GenericOOOIXU]>;
42+
def GenericOOOBranch : ProcResource<1>;
43+
def GenericOOOMulDiv : ProcResource<1>;
44+
def GenericOOOInt : ProcResource<2>;
45+
def GenericOOOALU
46+
: ProcResGroup<[GenericOOOBranch, GenericOOOMulDiv, GenericOOOInt]>;
4547
def GenericOOOLSU : ProcResource<2>;
46-
def GenericOOOFPU : ProcResource<2>;
48+
def GenericOOOFMulDiv : ProcResource<1>;
49+
def GenericOOOFloat : ProcResource<1>;
50+
def GenericOOOFPU : ProcResGroup<[GenericOOOFMulDiv, GenericOOOFloat]>;
4751
// TODO: Add vector scheduling.
4852
// def GenericOOOVXU : ProcResource<1>;
4953

5054
//===----------------------------------------------------------------------===//
5155
// Branches
5256
//===----------------------------------------------------------------------===//
53-
def : WriteRes<WriteJmp, [GenericOOOALU]>;
54-
def : WriteRes<WriteJalr, [GenericOOOALU]>;
55-
def : WriteRes<WriteJal, [GenericOOOALU]>;
57+
def : WriteRes<WriteJmp, [GenericOOOBranch]>;
58+
def : WriteRes<WriteJalr, [GenericOOOBranch]>;
59+
def : WriteRes<WriteJal, [GenericOOOBranch]>;
5660

5761
//===----------------------------------------------------------------------===//
5862
// Integer arithmetic and logic
@@ -68,26 +72,26 @@ def : WriteRes<WriteShiftReg32, [GenericOOOALU]>;
6872
// Integer multiplication
6973
//===----------------------------------------------------------------------===//
7074
let Latency = 4 in {
71-
def : WriteRes<WriteIMul, [GenericOOOALU]>;
72-
def : WriteRes<WriteIMul32, [GenericOOOALU]>;
75+
def : WriteRes<WriteIMul, [GenericOOOMulDiv]>;
76+
def : WriteRes<WriteIMul32, [GenericOOOMulDiv]>;
7377
}
7478

7579
//===----------------------------------------------------------------------===//
7680
// Integer division
7781
//===----------------------------------------------------------------------===//
78-
def : WriteRes<WriteIDiv32, [GenericOOODIV]> {
82+
def : WriteRes<WriteIDiv32, [GenericOOOMulDiv]> {
7983
let Latency = 13;
8084
let ReleaseAtCycles = [13];
8185
}
82-
def : WriteRes<WriteIDiv, [GenericOOODIV]> {
86+
def : WriteRes<WriteIDiv, [GenericOOOMulDiv]> {
8387
let Latency = 21;
8488
let ReleaseAtCycles = [21];
8589
}
86-
def : WriteRes<WriteIRem32, [GenericOOODIV]> {
90+
def : WriteRes<WriteIRem32, [GenericOOOMulDiv]> {
8791
let Latency = 13;
8892
let ReleaseAtCycles = [13];
8993
}
90-
def : WriteRes<WriteIRem, [GenericOOODIV]> {
94+
def : WriteRes<WriteIRem, [GenericOOOMulDiv]> {
9195
let Latency = 21;
9296
let ReleaseAtCycles = [21];
9397
}
@@ -144,16 +148,6 @@ let Latency = 2 in {
144148
def : WriteRes<WriteFAdd64, [GenericOOOFPU]>;
145149
}
146150

147-
let Latency = 4 in {
148-
def : WriteRes<WriteFMul32, [GenericOOOFPU]>;
149-
def : WriteRes<WriteFMul64, [GenericOOOFPU]>;
150-
}
151-
152-
let Latency = 6 in {
153-
def : WriteRes<WriteFMA32, [GenericOOOFPU]>;
154-
def : WriteRes<WriteFMA64, [GenericOOOFPU]>;
155-
}
156-
157151
def : WriteRes<WriteFSGNJ32, [GenericOOOFPU]>;
158152
def : WriteRes<WriteFSGNJ64, [GenericOOOFPU]>;
159153
def : WriteRes<WriteFMinMax32, [GenericOOOFPU]>;
@@ -165,15 +159,27 @@ let Latency = 2 in {
165159
def : WriteRes<WriteFCmp64, [GenericOOOFPU]>;
166160
}
167161

162+
// Multiplication
163+
let Latency = 4 in {
164+
def : WriteRes<WriteFMul32, [GenericOOOFMulDiv]>;
165+
def : WriteRes<WriteFMul64, [GenericOOOFMulDiv]>;
166+
}
167+
168+
// FMA
169+
let Latency = 6 in {
170+
def : WriteRes<WriteFMA32, [GenericOOOFMulDiv]>;
171+
def : WriteRes<WriteFMA64, [GenericOOOFMulDiv]>;
172+
}
173+
168174
// Division
169175
let Latency = 13, ReleaseAtCycles = [13] in {
170-
def : WriteRes<WriteFDiv32, [GenericOOOFPU]>;
171-
def : WriteRes<WriteFSqrt32, [GenericOOOFPU]>;
176+
def : WriteRes<WriteFDiv32, [GenericOOOFMulDiv]>;
177+
def : WriteRes<WriteFSqrt32, [GenericOOOFMulDiv]>;
172178
}
173179

174180
let Latency = 17, ReleaseAtCycles = [17] in {
175-
def : WriteRes<WriteFDiv64, [GenericOOOFPU]>;
176-
def : WriteRes<WriteFSqrt64, [GenericOOOFPU]>;
181+
def : WriteRes<WriteFDiv64, [GenericOOOFMulDiv]>;
182+
def : WriteRes<WriteFSqrt64, [GenericOOOFMulDiv]>;
177183
}
178184

179185
// Conversions

0 commit comments

Comments
 (0)