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topperctopperc
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fixup! Support MakeCompressible
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‎llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -433,6 +433,11 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
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BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::PseudoMV_FPR16INX),
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NewReg)
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.addReg(RegImm.Reg);
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} else if (RISCV::GPRF32RegClass.contains(RegImm.Reg)) {
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assert(RegImm.Imm == 0);
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BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::PseudoMV_FPR32INX),
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NewReg)
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.addReg(RegImm.Reg);
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} else {
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// If we are looking at replacing an FPR register we don't expect to
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// have any offset. The only compressible FP instructions with an offset

‎llvm/test/CodeGen/RISCV/make-compressible-zfinx.mir‎

Lines changed: 296 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,296 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=riscv32 -mattr=+c,+zfinx -simplify-mir \
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# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s
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# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+zfinx -simplify-mir \
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# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=CHECK %s
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--- |
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define void @store_common_value_float(ptr %a, ptr %b, ptr %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j) #0 {
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entry:
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store float %j, ptr %a, align 4
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store float %j, ptr %b, align 4
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store float %j, ptr %c, align 4
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ret void
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}
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define void @store_common_ptr_float(float %a, float %b, float %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, ptr %p) #0 {
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entry:
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store volatile float %a, ptr %p, align 4
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store volatile float %b, ptr %p, align 4
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store volatile float %c, ptr %p, align 4
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ret void
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}
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define void @load_common_ptr_float(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 {
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entry:
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%0 = load float, ptr %g, align 4
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%arrayidx1 = getelementptr inbounds float, ptr %g, i32 1
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%1 = load float, ptr %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds float, ptr %g, i32 2
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%2 = load float, ptr %arrayidx2, align 4
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tail call void @load_common_ptr_float_1(float %0, float %1, float %2)
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ret void
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}
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declare void @load_common_ptr_float_1(float, float, float) #0
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define void @store_large_offset_float(ptr %p, float %a, float %b, float %c, float %d) #0 {
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entry:
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%0 = getelementptr inbounds float, ptr %p, i32 100
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store volatile float %a, ptr %0, align 4
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%1 = getelementptr inbounds float, ptr %p, i32 101
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store volatile float %b, ptr %1, align 4
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%2 = getelementptr inbounds float, ptr %p, i32 102
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store volatile float %c, ptr %2, align 4
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%3 = getelementptr inbounds float, ptr %p, i32 103
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store volatile float %d, ptr %3, align 4
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ret void
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}
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define void @load_large_offset_float(ptr %p) #0 {
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entry:
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%arrayidx = getelementptr inbounds float, ptr %p, i32 100
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%0 = load float, ptr %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds float, ptr %p, i32 101
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%1 = load float, ptr %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds float, ptr %p, i32 102
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%2 = load float, ptr %arrayidx2, align 4
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tail call void @load_large_offset_float_1(float %0, float %1, float %2)
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ret void
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}
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declare void @load_large_offset_float_1(float, float, float) #0
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define void @store_common_value_float_no_opt(ptr %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h) #0 {
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entry:
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store float %h, ptr %a, align 4
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ret void
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}
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define void @store_common_ptr_float_no_opt(float %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, ptr %p) #0 {
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entry:
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store volatile float %a, ptr %p, align 4
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ret void
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}
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define float @load_common_ptr_float_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 {
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entry:
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%0 = load float, ptr %g, align 4
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ret float %0
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}
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define void @store_large_offset_float_no_opt(ptr %p, float %a, float %b) #0 {
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entry:
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%0 = getelementptr inbounds float, ptr %p, i32 100
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store volatile float %a, ptr %0, align 4
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%1 = getelementptr inbounds float, ptr %p, i32 101
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store volatile float %b, ptr %1, align 4
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ret void
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}
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define { float, float } @load_large_offset_float_no_opt(ptr %p) #0 {
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entry:
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%arrayidx = getelementptr inbounds float, ptr %p, i32 100
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%0 = load float, ptr %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds float, ptr %p, i32 101
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%1 = load float, ptr %arrayidx1, align 4
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%2 = insertvalue { float, float } undef, float %0, 0
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%3 = insertvalue { float, float } %2, float %1, 1
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ret { float, float } %3
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}
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attributes #0 = { minsize }
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...
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---
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name: store_common_value_float
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12
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; CHECK-LABEL: name: store_common_value_float
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; CHECK: liveins: $x10, $x11, $x12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x13_w = PseudoMV_FPR32INX $x0_w
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; CHECK-NEXT: SW_INX $x13_w, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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; CHECK-NEXT: SW_INX $x13_w, killed renamable $x11, 0 :: (store (s32) into %ir.b)
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; CHECK-NEXT: SW_INX killed $x13_w, killed renamable $x12, 0 :: (store (s32) into %ir.c)
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; CHECK-NEXT: PseudoRET
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SW_INX $x0_w, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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SW_INX $x0_w, killed renamable $x11, 0 :: (store (s32) into %ir.b)
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SW_INX killed $x0_w, killed renamable $x12, 0 :: (store (s32) into %ir.c)
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PseudoRET
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...
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---
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name: store_common_ptr_float
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10_w, $x11_w, $x12_w, $x16
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; CHECK-LABEL: name: store_common_ptr_float
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; CHECK: liveins: $x10_w, $x11_w, $x12_w, $x16
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x13 = ADDI $x16, 0
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; CHECK-NEXT: SW_INX killed renamable $x10_w, $x13, 0 :: (volatile store (s32) into %ir.p)
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; CHECK-NEXT: SW_INX killed renamable $x11_w, $x13, 0 :: (volatile store (s32) into %ir.p)
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; CHECK-NEXT: SW_INX killed renamable $x12_w, killed $x13, 0 :: (volatile store (s32) into %ir.p)
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; CHECK-NEXT: PseudoRET
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SW_INX killed renamable $x10_w, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
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SW_INX killed renamable $x11_w, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
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SW_INX killed renamable $x12_w, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
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PseudoRET
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...
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---
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name: load_common_ptr_float
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x16
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; CHECK-LABEL: name: load_common_ptr_float
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; CHECK: liveins: $x16
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x13 = ADDI $x16, 0
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; CHECK-NEXT: renamable $x10_w = LW_INX $x13, 0 :: (load (s32) from %ir.g)
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; CHECK-NEXT: renamable $x11_w = LW_INX $x13, 4 :: (load (s32) from %ir.arrayidx1)
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; CHECK-NEXT: renamable $x12_w = LW_INX killed $x13, 8 :: (load (s32) from %ir.arrayidx2)
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; CHECK-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $x10_w, implicit $x11_w, implicit $x12_w
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renamable $x10_w = LW_INX renamable $x16, 0 :: (load (s32) from %ir.g)
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renamable $x11_w = LW_INX renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
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renamable $x12_w = LW_INX killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
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PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $x10_w, implicit $x11_w, implicit $x12_w
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...
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---
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name: store_large_offset_float
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11_w, $x11_w, $x12_w, $x13_w
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; CHECK-LABEL: name: store_large_offset_float
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; CHECK: liveins: $x10, $x11_w, $x11_w, $x12_w, $x13_w
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x14 = ADDI $x10, 384
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; CHECK-NEXT: SW_INX killed renamable $x10_w, $x14, 16 :: (volatile store (s32) into %ir.0)
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; CHECK-NEXT: SW_INX killed renamable $x11_w, $x14, 20 :: (volatile store (s32) into %ir.1)
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; CHECK-NEXT: SW_INX killed renamable $x12_w, $x14, 24 :: (volatile store (s32) into %ir.2)
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; CHECK-NEXT: SW_INX killed renamable $x13_w, killed $x14, 28 :: (volatile store (s32) into %ir.3)
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; CHECK-NEXT: PseudoRET
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SW_INX killed renamable $x10_w, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
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SW_INX killed renamable $x11_w, renamable $x10, 404 :: (volatile store (s32) into %ir.1)
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SW_INX killed renamable $x12_w, renamable $x10, 408 :: (volatile store (s32) into %ir.2)
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SW_INX killed renamable $x13_w, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3)
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PseudoRET
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...
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---
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name: load_large_offset_float
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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; CHECK-LABEL: name: load_large_offset_float
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x14 = ADDI $x10, 384
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; CHECK-NEXT: renamable $x11_w = LW_INX $x14, 16 :: (load (s32) from %ir.arrayidx)
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; CHECK-NEXT: renamable $x12_w = LW_INX $x14, 20 :: (load (s32) from %ir.arrayidx1)
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; CHECK-NEXT: renamable $x13_w = LW_INX killed $x14, 24 :: (load (s32) from %ir.arrayidx2)
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; CHECK-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $x11_w, implicit $x12_w, implicit $x12_w
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renamable $x11_w = LW_INX renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
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renamable $x12_w = LW_INX renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
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renamable $x13_w = LW_INX killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
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PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $x11_w, implicit $x12_w, implicit $x12_w
211+
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...
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---
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name: store_common_value_float_no_opt
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x16_w
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; CHECK-LABEL: name: store_common_value_float_no_opt
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; CHECK: liveins: $x10, $x16_w
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SW_INX killed renamable $x16_w, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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; CHECK-NEXT: PseudoRET
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SW_INX killed renamable $x16_w, killed renamable $x10, 0 :: (store (s32) into %ir.a)
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PseudoRET
227+
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...
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---
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name: store_common_ptr_float_no_opt
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x16, $x10_w
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236+
; CHECK-LABEL: name: store_common_ptr_float_no_opt
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; CHECK: liveins: $x16, $x10_w
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SW_INX killed renamable $x10_w, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
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; CHECK-NEXT: PseudoRET
241+
SW_INX killed renamable $x10_w, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
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PseudoRET
243+
244+
...
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---
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name: load_common_ptr_float_no_opt
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tracksRegLiveness: true
248+
body: |
249+
bb.0.entry:
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liveins: $x16
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; CHECK-LABEL: name: load_common_ptr_float_no_opt
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; CHECK: liveins: $x16
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x10_w = LW_INX killed renamable $x16, 0 :: (load (s32) from %ir.g)
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; CHECK-NEXT: PseudoRET implicit $x10_w
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renamable $x10_w = LW_INX killed renamable $x16, 0 :: (load (s32) from %ir.g)
258+
PseudoRET implicit $x10_w
259+
260+
...
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---
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name: store_large_offset_float_no_opt
263+
tracksRegLiveness: true
264+
body: |
265+
bb.0.entry:
266+
liveins: $x10, $x11_w, $x12_w
267+
268+
; CHECK-LABEL: name: store_large_offset_float_no_opt
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; CHECK: liveins: $x10, $x11_w, $x12_w
270+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SW_INX killed renamable $x11_w, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
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; CHECK-NEXT: SW_INX killed renamable $x12_w, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
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; CHECK-NEXT: PseudoRET
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SW_INX killed renamable $x11_w, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
275+
SW_INX killed renamable $x12_w, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
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PseudoRET
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278+
...
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---
280+
name: load_large_offset_float_no_opt
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tracksRegLiveness: true
282+
body: |
283+
bb.0.entry:
284+
liveins: $x10
285+
286+
; CHECK-LABEL: name: load_large_offset_float_no_opt
287+
; CHECK: liveins: $x10
288+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x11_w = LW_INX renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
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; CHECK-NEXT: renamable $x12_w = LW_INX killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
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; CHECK-NEXT: PseudoRET implicit $x11_w, implicit $x12_w
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renamable $x11_w = LW_INX renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
293+
renamable $x12_w = LW_INX killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
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PseudoRET implicit $x11_w, implicit $x12_w
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...

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