[Fix] Avoid change the register pressure.

Author: link-xyq

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

@@ -788,7 +788,9 @@ def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
 def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0), 1>;
 
 def VREven : VReg<!listconcat(VM1VTs, VMaskVTs),
-                  (add (sequence "V%u", 0, 30, 2)), 1>;
+                  (add (sequence "V%u", 0, 30, 2)), 1>{
+  let GeneratePressureSet = 0;
+}
 
 def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
                              (sequence "V%uM2", 6, 0, 2)), 2>;

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

@@ -1220,9 +1220,9 @@ define void @mgather_nxv16i64(<vscale x 8 x ptr> %ptrs0, <vscale x 8 x ptr> %ptr
 ; RV32-LABEL: mgather_nxv16i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vl8re64.v v24, (a0)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    vluxei32.v v16, (zero), v8, v0.t
 ; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
+; RV32-NEXT:    vluxei32.v v16, (zero), v8, v0.t
 ; RV32-NEXT:    srli a2, a0, 3
 ; RV32-NEXT:    vsetvli a3, zero, e8, mf4, ta, ma
 ; RV32-NEXT:    vslidedown.vx v0, v0, a2