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1 | 1 | // RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ |
2 | 2 | // RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \ |
3 | | -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL |
| 3 | +// RUN: FileCheck %s --check-prefixes=CHECK,DXCHECK |
| 4 | + |
4 | 5 | // RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ |
5 | 6 | // RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \ |
6 | | -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV |
| 7 | +// RUN: FileCheck %s --check-prefixes=CHECK,SPVCHECK |
| 8 | + |
| 9 | +// DXCHECK: define hidden [[FN_TYPE:]]noundef i1 @ |
| 10 | +// SPVCHECK: define hidden [[FN_TYPE:spir_func ]]noundef i1 @ |
7 | 11 |
|
8 | 12 | // Test basic lowering to runtime function call. |
9 | 13 |
|
10 | 14 | // CHECK-LABEL: test_uint |
11 | 15 | uint test_uint(uint expr) { |
12 | | - // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.or.i32([[TY]] %[[#]]) |
13 | | - // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.or.i32([[TY]] %[[#]]) |
| 16 | + // DXCHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i32([[TY]] %[[#]]) |
| 17 | + // SPVCHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]]) |
14 | 18 | // CHECK: ret [[TY]] %[[RET]] |
15 | 19 | return WaveActiveBitOr(expr); |
16 | 20 | } |
17 | 21 |
|
18 | | -// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.or.i32([[TY]]) #[[#attr:]] |
19 | | -// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.or.i32([[TY]]) #[[#attr:]] |
| 22 | +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i32([[TY]]) #[[#attr:]] |
20 | 23 |
|
21 | 24 | // CHECK-LABEL: test_uint64_t |
22 | 25 | uint64_t test_uint64_t(uint64_t expr) { |
23 | | - // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.or.i64([[TY]] %[[#]]) |
24 | | - // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.or.i64([[TY]] %[[#]]) |
| 26 | + // CHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]] %[[#]]) |
25 | 27 | // CHECK: ret [[TY]] %[[RET]] |
26 | 28 | return WaveActiveBitOr(expr); |
27 | 29 | } |
28 | 30 |
|
29 | | -// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.or.i64([[TY]]) #[[#attr:]] |
30 | | -// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.or.i64([[TY]]) #[[#attr:]] |
| 31 | +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]]) #[[#attr:]] |
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