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Address review feedback.
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‎llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp‎

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@@ -1927,8 +1927,6 @@ class MFMASmallGemmSingleWaveOpt final : public IGLPStrategy {
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return FitsInGroup;
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}
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assert(Cache->size());
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// Does the VALU have a DS_WRITE successor that is the same as other
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// VALU already in the group. The V_PERMs will all share 1 DS_W succ
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return llvm::any_of(*Cache, [&SU](SUnit *Elt) {

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll‎

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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O1 -global-isel=true < %s
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; Function Attrs: nounwind
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define amdgpu_kernel void @test_iglp_opt() #0 {
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entry:
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call void @llvm.amdgcn.iglp.opt(i32 0) #4
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ret void
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}
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; Function Attrs: nounwind
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define amdgpu_kernel void @test_iglp_opt_mfma_gemm(ptr addrspace(3) noalias %in, ptr addrspace(3) noalias %out) #0 {
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entry:
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call void @llvm.amdgcn.iglp.opt(i32 0)
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%idx = call i32 @llvm.amdgcn.workitem.id.x()
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%load.0.addr = getelementptr <32 x float>, ptr addrspace(3) %in, i32 %idx
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%load.0 = load <32 x float>, ptr addrspace(3) %load.0.addr, align 128
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%load.1.addr = getelementptr <32 x float>, ptr addrspace(3) %load.0.addr, i32 64
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%load.1 = load <32 x float>, ptr addrspace(3) %load.1.addr, align 128
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%load.2.addr = getelementptr <32 x float>, ptr addrspace(3) %load.1.addr, i32 128
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%load.2 = load <32 x float>, ptr addrspace(3) %load.2.addr, align 128
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%load.3.addr = getelementptr <32 x float>, ptr addrspace(3) %load.2.addr, i32 192
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%load.3 = load <32 x float>, ptr addrspace(3) %load.3.addr, align 128
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%load.4.addr = getelementptr <32 x float>, ptr addrspace(3) %load.3.addr, i32 256
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%load.4 = load <32 x float>, ptr addrspace(3) %load.4.addr, align 128
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%mai.0 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.0, i32 0, i32 0, i32 0)
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%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.1, i32 0, i32 0, i32 0)
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%mai.2 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.2, i32 0, i32 0, i32 0)
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%mai.3 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.3, i32 0, i32 0, i32 0)
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%mai.4 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.4, i32 0, i32 0, i32 0)
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%store.0.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 %idx
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store <32 x float> %mai.0, ptr addrspace(3) %store.0.addr, align 128
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%store.1.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 64
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store <32 x float> %mai.1, ptr addrspace(3) %store.1.addr, align 128
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%store.2.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 128
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store <32 x float> %mai.2, ptr addrspace(3) %store.2.addr, align 128
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%store.3.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 192
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store <32 x float> %mai.3, ptr addrspace(3) %store.3.addr, align 128
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%store.4.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 256
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store <32 x float> %mai.4, ptr addrspace(3) %store.4.addr, align 128
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ret void
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}
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; Function Attrs: nounwind
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define amdgpu_kernel void @test_iglp_opt_rev_mfma_gemm(ptr addrspace(3) noalias %in, ptr addrspace(3) noalias %out) #0 {
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entry:
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call void @llvm.amdgcn.iglp.opt(i32 1)
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%idx = call i32 @llvm.amdgcn.workitem.id.x()
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%load.0.addr = getelementptr <32 x float>, ptr addrspace(3) %in, i32 %idx
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%load.0 = load <32 x float>, ptr addrspace(3) %load.0.addr, align 128
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%load.1.addr = getelementptr <32 x float>, ptr addrspace(3) %load.0.addr, i32 64
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%load.1 = load <32 x float>, ptr addrspace(3) %load.1.addr, align 128
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%load.2.addr = getelementptr <32 x float>, ptr addrspace(3) %load.1.addr, i32 128
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%load.2 = load <32 x float>, ptr addrspace(3) %load.2.addr, align 128
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%load.3.addr = getelementptr <32 x float>, ptr addrspace(3) %load.2.addr, i32 192
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%L = load <1 x i64>, ptr addrspace(3) %load.3.addr, align 8
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%load.3 = load <32 x float>, ptr addrspace(3) %load.3.addr, align 128
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%load.4.addr = getelementptr <32 x float>, ptr addrspace(3) %load.3.addr, i32 256
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%L1 = load <1 x i64>, ptr addrspace(3) %load.4.addr, align 8
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%load.4 = load <32 x float>, ptr addrspace(3) %load.4.addr, align 128
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%B = urem <1 x i64> %L, %L1
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%mai.0 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.0, i32 0, i32 0, i32 0)
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%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.1, i32 0, i32 0, i32 0)
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%mai.2 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.2, i32 0, i32 0, i32 0)
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%mai.3 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.3, i32 0, i32 0, i32 0)
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%mai.4 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %load.4, i32 0, i32 0, i32 0)
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%store.0.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 %idx
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store <32 x float> %mai.0, ptr addrspace(3) %store.0.addr, align 128
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%store.1.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 64
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store <32 x float> %mai.1, ptr addrspace(3) %store.1.addr, align 128
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%store.2.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 128
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store <32 x float> %mai.2, ptr addrspace(3) %store.2.addr, align 128
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%store.3.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 192
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store <32 x float> %mai.3, ptr addrspace(3) %store.3.addr, align 128
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%store.4.addr = getelementptr <32 x float>, ptr addrspace(3) %out, i32 256
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store <32 x float> %mai.4, ptr addrspace(3) %store.4.addr, align 128
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store <1 x i64> %B, ptr addrspace(3) %store.3.addr, align 8
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ret void
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}
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; Function Attrs: convergent nocallback nofree nounwind willreturn
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declare void @llvm.amdgcn.iglp.opt(i32 immarg) #1
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32 immarg, i32 immarg, i32 immarg) #3
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attributes #0 = { nounwind "amdgpu-flat-work-group-size"="1,256" }
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attributes #1 = { convergent nocallback nofree nounwind willreturn }
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attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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attributes #3 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #4 = { convergent nounwind }

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