[RISCV] Delay the transform so that vwsll has priority

Author: pfusik

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -17343,16 +17343,16 @@ static SDValue combineScalarCTPOPToVCPOP(SDNode *N, SelectionDAG &DAG,
 
 static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                           const RISCVSubtarget &Subtarget) {
-  if (DCI.isBeforeLegalize())
-    return SDValue();
-
   // (shl (zext x), y) -> (vwsll   x, y)
   if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
     return V;
 
   // (shl (sext x), C) -> (vwmulsu x, 1u << C)
   // (shl (zext x), C) -> (vwmulu  x, 1u << C)
 
+  if (!DCI.isAfterLegalizeDAG())
+    return SDValue();
+
   SDValue LHS = N->getOperand(0);
   if (!LHS.hasOneUse())
     return SDValue();

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll

@@ -441,20 +441,12 @@ define <8 x i32> @vwsll_vi_v8i32(<8 x i16> %a) {
 ; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
 ;
-; CHECK-ZVBB-RV32-LABEL: vwsll_vi_v8i32:
-; CHECK-ZVBB-RV32:       # %bb.0:
-; CHECK-ZVBB-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-ZVBB-RV32-NEXT:    vwsll.vi v10, v8, 2
-; CHECK-ZVBB-RV32-NEXT:    vmv2r.v v8, v10
-; CHECK-ZVBB-RV32-NEXT:    ret
-;
-; CHECK-ZVBB-RV64-LABEL: vwsll_vi_v8i32:
-; CHECK-ZVBB-RV64:       # %bb.0:
-; CHECK-ZVBB-RV64-NEXT:    li a0, 4
-; CHECK-ZVBB-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-ZVBB-RV64-NEXT:    vwmulu.vx v10, v8, a0
-; CHECK-ZVBB-RV64-NEXT:    vmv2r.v v8, v10
-; CHECK-ZVBB-RV64-NEXT:    ret
+; CHECK-ZVBB-LABEL: vwsll_vi_v8i32:
+; CHECK-ZVBB:       # %bb.0:
+; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
+; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
+; CHECK-ZVBB-NEXT:    ret
   %x = zext <8 x i16> %a to <8 x i32>
   %z = shl <8 x i32> %x, splat (i32 2)
   ret <8 x i32> %z
@@ -672,9 +664,8 @@ define <16 x i16> @vwsll_vi_v16i16(<16 x i8> %a) {
 ;
 ; CHECK-ZVBB-LABEL: vwsll_vi_v16i16:
 ; CHECK-ZVBB:       # %bb.0:
-; CHECK-ZVBB-NEXT:    li a0, 4
 ; CHECK-ZVBB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-ZVBB-NEXT:    vwmulu.vx v10, v8, a0
+; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
 ; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
 ; CHECK-ZVBB-NEXT:    ret
   %x = zext <16 x i8> %a to <16 x i16>