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‎llvm/test/CodeGen/RISCV/machine-outliner-call-x5-liveout.mir‎

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV32I-MO %s
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# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV64I-MO %s
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# MIR has been edited by hand to have x5 as live out in @dont_outline
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--- |
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define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 }
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; Can't outline if x5 is live out of the MBB
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define i32 @dont_outline(i32 %a, i32 %b) { ret i32 0 }
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define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 }
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define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 }
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...
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---
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name: outline_0
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tracksRegLiveness: true
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isOutlined: false
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: outline_0
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET implicit $x11
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;
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; RV64I-MO-LABEL: name: outline_0
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET implicit $x11
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x11
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...
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---
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name: dont_outline
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tracksRegLiveness: true
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isOutlined: false
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body: |
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; RV32I-MO-LABEL: name: dont_outline
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; RV32I-MO: bb.0:
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; RV32I-MO-NEXT: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: BEQ $x10, $x11, %bb.1
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: bb.1:
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; RV32I-MO-NEXT: liveins: $x10, $x5
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: PseudoRET implicit $x10, implicit $x5
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;
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; RV64I-MO-LABEL: name: dont_outline
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; RV64I-MO: bb.0:
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; RV64I-MO-NEXT: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: BEQ $x10, $x11, %bb.1
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: bb.1:
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; RV64I-MO-NEXT: liveins: $x10, $x5
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: PseudoRET implicit $x10, implicit $x5
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bb.0:
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liveins: $x10, $x11
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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BEQ $x10, $x11, %bb.1
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bb.1:
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liveins: $x10, $x5
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PseudoRET implicit $x10, implicit $x5
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...
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---
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name: outline_1
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tracksRegLiveness: true
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isOutlined: false
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: outline_1
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET implicit $x10
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;
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; RV64I-MO-LABEL: name: outline_1
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET implicit $x10
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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---
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name: outline_2
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tracksRegLiveness: true
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isOutlined: false
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: outline_2
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET implicit $x12
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;
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; RV64I-MO-LABEL: name: outline_2
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET implicit $x12
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x12
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...

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