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PankajDwivedi-25PankajDwivedi-25
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added pass to llc pipeline
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‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -1222,6 +1222,8 @@ void AMDGPUPassConfig::addIRPasses() {
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if (isPassEnabled(EnableImageIntrinsicOptimizer))
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addPass(createAMDGPUImageIntrinsicOptimizerPass(&TM));
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if (EnableUniformIntrinsicCombine)
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addPass(createAMDGPUUniformIntrinsicCombineLegacyPass());
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// This can be disabled by passing ::Disable here or on the command line
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// with --expand-variadics-override=disable.
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addPass(createExpandVariadicsPass(ExpandVariadicsMode::Lowering));

‎llvm/test/CodeGen/AMDGPU/amdgpu-miscellaneous-uniform-intrinsics.ll‎

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@@ -0,0 +1,131 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck %s
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define amdgpu_kernel void @readfirstlane_with_readfirstlane(ptr addrspace(1) %out) {
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; CHECK-LABEL: readfirstlane_with_readfirstlane:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 5
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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%v1 = call i32 @llvm.amdgcn.readfirstlane(i32 5)
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%v2 = call i32 @llvm.amdgcn.readfirstlane(i32 %v1)
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store i32 %v2, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @readfirstlane_with_readlane(ptr addrspace(1) %out) {
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; CHECK-LABEL: readfirstlane_with_readlane:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: v_bfe_u32 v1, v0, 10, 10
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_readfirstlane_b32 s2, v1
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; CHECK-NEXT: v_readlane_b32 s2, v0, s2
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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%tidx = call i32 @llvm.amdgcn.workitem.id.x()
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%tidy = call i32 @llvm.amdgcn.workitem.id.y()
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%v1 = call i32 @llvm.amdgcn.readlane(i32 %tidx, i32 %tidy)
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%v2 = call i32 @llvm.amdgcn.readfirstlane(i32 %v1)
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store i32 %v2, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @readlane_with_firstlane(ptr addrspace(1) %out) {
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; CHECK-LABEL: readlane_with_firstlane:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_readfirstlane_b32 s2, v0
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; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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%tidx = call i32 @llvm.amdgcn.workitem.id.x()
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%v1 = call i32 @llvm.amdgcn.readfirstlane(i32 %tidx)
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%v2 = call i32 @llvm.amdgcn.readlane(i32 %v1, i32 3)
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store i32 %v2, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @readlane_readlane(ptr addrspace(1) %out) {
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; CHECK-LABEL: readlane_readlane:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: v_bfe_u32 v1, v0, 10, 10
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_readfirstlane_b32 s2, v1
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; CHECK-NEXT: v_readlane_b32 s2, v0, s2
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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%tidx = call i32 @llvm.amdgcn.workitem.id.x()
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%tidy = call i32 @llvm.amdgcn.workitem.id.y()
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%v1 = call i32 @llvm.amdgcn.readlane(i32 %tidx, i32 %tidy)
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%v2 = call i32 @llvm.amdgcn.readlane(i32 %v1, i32 2)
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store i32 %v2, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @permlane64_uniform(ptr addrspace(1) %out, i32 %src) {
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; CHECK-LABEL: permlane64_uniform:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_clause 0x1
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; CHECK-NEXT: s_load_b32 s2, s[4:5], 0x8
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
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; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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%v = call i32 @llvm.amdgcn.permlane64(i32 %src)
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store i32 %v, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @permlane64_nonuniform(i32 addrspace(1)* %out) {
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; CHECK-LABEL: permlane64_nonuniform:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; CHECK-NEXT: v_permlane64_b32 v1, v0
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; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%v = call i32 @llvm.amdgcn.permlane64(i32 %tid)
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%out_ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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store i32 %v, i32 addrspace(1)* %out_ptr
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ret void
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}
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define amdgpu_kernel void @permlane64_nonuniform_expression(i32 addrspace(1)* %out) {
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; CHECK-LABEL: permlane64_nonuniform_expression:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
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; CHECK-NEXT: v_add_nc_u32_e32 v1, 1, v0
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; CHECK-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; CHECK-NEXT: v_permlane64_b32 v1, v1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid2 = add i32 %tid, 1
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%v = call i32 @llvm.amdgcn.permlane64(i32 %tid2)
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%out_ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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store i32 %v, i32 addrspace(1)* %out_ptr
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ret void
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}

‎llvm/test/CodeGen/AMDGPU/llc-pipeline.ll‎

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Original file line numberDiff line numberDiff line change
@@ -31,6 +31,11 @@
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; GCN-O0-NEXT: AMDGPU Remove Incompatible Functions
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; GCN-O0-NEXT: AMDGPU Printf lowering
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; GCN-O0-NEXT: Lower ctors and dtors for AMDGPU
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; GCN-O0-NEXT: FunctionPass Manager
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; GCN-O0-NEXT: Dominator Tree Construction
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; GCN-O0-NEXT: Cycle Info Analysis
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; GCN-O0-NEXT: Uniformity Analysis
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; GCN-O0-NEXT: AMDGPU uniformIntrinsic Combine
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; GCN-O0-NEXT: Expand variadic functions
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; GCN-O0-NEXT: AMDGPU Inline All Functions
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; GCN-O0-NEXT: Inliner for always_inline functions
@@ -181,6 +186,11 @@
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; GCN-O1-NEXT: AMDGPU Remove Incompatible Functions
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; GCN-O1-NEXT: AMDGPU Printf lowering
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; GCN-O1-NEXT: Lower ctors and dtors for AMDGPU
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; GCN-O1-NEXT: FunctionPass Manager
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; GCN-O1-NEXT: Dominator Tree Construction
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; GCN-O1-NEXT: Cycle Info Analysis
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; GCN-O1-NEXT: Uniformity Analysis
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; GCN-O1-NEXT: AMDGPU uniformIntrinsic Combine
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; GCN-O1-NEXT: Expand variadic functions
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; GCN-O1-NEXT: AMDGPU Inline All Functions
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; GCN-O1-NEXT: Inliner for always_inline functions
@@ -466,6 +476,11 @@
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; GCN-O1-OPTS-NEXT: AMDGPU Remove Incompatible Functions
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; GCN-O1-OPTS-NEXT: AMDGPU Printf lowering
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; GCN-O1-OPTS-NEXT: Lower ctors and dtors for AMDGPU
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; GCN-O1-OPTS-NEXT: FunctionPass Manager
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; GCN-O1-OPTS-NEXT: Dominator Tree Construction
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; GCN-O1-OPTS-NEXT: Cycle Info Analysis
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; GCN-O1-OPTS-NEXT: Uniformity Analysis
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; GCN-O1-OPTS-NEXT: AMDGPU uniformIntrinsic Combine
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; GCN-O1-OPTS-NEXT: Expand variadic functions
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; GCN-O1-OPTS-NEXT: AMDGPU Inline All Functions
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; GCN-O1-OPTS-NEXT: Inliner for always_inline functions
@@ -781,6 +796,10 @@
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; GCN-O2-NEXT: Lower ctors and dtors for AMDGPU
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; GCN-O2-NEXT: FunctionPass Manager
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; GCN-O2-NEXT: AMDGPU Image Intrinsic Optimizer
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; GCN-O2-NEXT: Dominator Tree Construction
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; GCN-O2-NEXT: Cycle Info Analysis
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; GCN-O2-NEXT: Uniformity Analysis
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; GCN-O2-NEXT: AMDGPU uniformIntrinsic Combine
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; GCN-O2-NEXT: Expand variadic functions
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; GCN-O2-NEXT: AMDGPU Inline All Functions
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; GCN-O2-NEXT: Inliner for always_inline functions
@@ -1100,6 +1119,10 @@
11001119
; GCN-O3-NEXT: Lower ctors and dtors for AMDGPU
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; GCN-O3-NEXT: FunctionPass Manager
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; GCN-O3-NEXT: AMDGPU Image Intrinsic Optimizer
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; GCN-O3-NEXT: Dominator Tree Construction
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; GCN-O3-NEXT: Cycle Info Analysis
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; GCN-O3-NEXT: Uniformity Analysis
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; GCN-O3-NEXT: AMDGPU uniformIntrinsic Combine
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; GCN-O3-NEXT: Expand variadic functions
11041127
; GCN-O3-NEXT: AMDGPU Inline All Functions
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; GCN-O3-NEXT: Inliner for always_inline functions

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