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[InstCombine] Handle mixsize consecutive loads
1 parent 343b383 commit 16243e2

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3 files changed

+190
-179
lines changed

3 files changed

+190
-179
lines changed

‎llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -678,7 +678,7 @@ static bool foldLoadsRecursive(Value *V, LoadOps &LOps, const DataLayout &DL,
678678
// Verify if both loads have same base pointers and load sizes are same.
679679
uint64_t LoadSize1 = LI1->getType()->getPrimitiveSizeInBits();
680680
uint64_t LoadSize2 = LI2->getType()->getPrimitiveSizeInBits();
681-
if (Load1Ptr != Load2Ptr || LoadSize1 != LoadSize2)
681+
if (Load1Ptr != Load2Ptr)
682682
return false;
683683

684684
// Support Loadsizes greater or equal to 8bits and only power of 2.

‎llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll‎

Lines changed: 131 additions & 103 deletions
Original file line numberDiff line numberDiff line change
@@ -1529,20 +1529,24 @@ define i64 @eggs(ptr noundef readonly %arg) {
15291529
}
15301530

15311531
define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
1532-
; ALL-LABEL: @loadCombine_4consecutive_mixsize1(
1533-
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1534-
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1535-
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1536-
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1537-
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1538-
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1539-
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1540-
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1541-
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
1542-
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1543-
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1544-
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1545-
; ALL-NEXT: ret i32 [[O2]]
1532+
; LE-LABEL: @loadCombine_4consecutive_mixsize1(
1533+
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
1534+
; LE-NEXT: ret i32 [[L1]]
1535+
;
1536+
; BE-LABEL: @loadCombine_4consecutive_mixsize1(
1537+
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1538+
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1539+
; BE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1540+
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1541+
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1542+
; BE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1543+
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1544+
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1545+
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
1546+
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1547+
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1548+
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1549+
; BE-NEXT: ret i32 [[O2]]
15461550
;
15471551
%p1 = getelementptr i8, ptr %p, i32 2
15481552
%p2 = getelementptr i8, ptr %p, i32 3
@@ -1563,20 +1567,24 @@ define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
15631567
}
15641568

15651569
define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
1566-
; ALL-LABEL: @loadCombine_4consecutive_mixsize1_BE(
1567-
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1568-
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1569-
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1570-
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1571-
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1572-
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1573-
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1574-
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1575-
; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
1576-
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1577-
; ALL-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
1578-
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E3]]
1579-
; ALL-NEXT: ret i32 [[O2]]
1570+
; LE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
1571+
; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1572+
; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1573+
; LE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1574+
; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1575+
; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1576+
; LE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1577+
; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1578+
; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1579+
; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
1580+
; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1581+
; LE-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
1582+
; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E3]]
1583+
; LE-NEXT: ret i32 [[O2]]
1584+
;
1585+
; BE-LABEL: @loadCombine_4consecutive_mixsize1_BE(
1586+
; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
1587+
; BE-NEXT: ret i32 [[L1]]
15801588
;
15811589
%p1 = getelementptr i8, ptr %p, i32 2
15821590
%p2 = getelementptr i8, ptr %p, i32 3
@@ -1597,20 +1605,24 @@ define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
15971605
}
15981606

15991607
define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
1600-
; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1(
1601-
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1602-
; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
1603-
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1604-
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
1605-
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
1606-
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1607-
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1608-
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1609-
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
1610-
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1611-
; ALL-NEXT: [[O1:%.*]] = or i32 [[S3]], [[S2]]
1612-
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E1]]
1613-
; ALL-NEXT: ret i32 [[O2]]
1608+
; LE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
1609+
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
1610+
; LE-NEXT: ret i32 [[L1]]
1611+
;
1612+
; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1(
1613+
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1614+
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
1615+
; BE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1616+
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
1617+
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
1618+
; BE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1619+
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1620+
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1621+
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
1622+
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1623+
; BE-NEXT: [[O1:%.*]] = or i32 [[S3]], [[S2]]
1624+
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E1]]
1625+
; BE-NEXT: ret i32 [[O2]]
16141626
;
16151627
%p2 = getelementptr i8, ptr %p, i32 2
16161628
%p3 = getelementptr i8, ptr %p, i32 3
@@ -1631,20 +1643,24 @@ define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
16311643
}
16321644

16331645
define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
1634-
; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
1635-
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1636-
; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
1637-
; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1638-
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
1639-
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
1640-
; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1641-
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1642-
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1643-
; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
1644-
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1645-
; ALL-NEXT: [[O1:%.*]] = or i32 [[E3]], [[S2]]
1646-
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S1]]
1647-
; ALL-NEXT: ret i32 [[O2]]
1646+
; LE-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
1647+
; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
1648+
; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
1649+
; LE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
1650+
; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
1651+
; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
1652+
; LE-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
1653+
; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1654+
; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1655+
; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
1656+
; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1657+
; LE-NEXT: [[O1:%.*]] = or i32 [[E3]], [[S2]]
1658+
; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S1]]
1659+
; LE-NEXT: ret i32 [[O2]]
1660+
;
1661+
; BE-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
1662+
; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 2
1663+
; BE-NEXT: ret i32 [[L1]]
16481664
;
16491665
%p2 = getelementptr i8, ptr %p, i32 2
16501666
%p3 = getelementptr i8, ptr %p, i32 3
@@ -1665,20 +1681,24 @@ define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
16651681
}
16661682

16671683
define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
1668-
; ALL-LABEL: @loadCombine_4consecutive_mixsize2(
1669-
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1670-
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
1671-
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1672-
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1673-
; ALL-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
1674-
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1675-
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1676-
; ALL-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i32
1677-
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1678-
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
1679-
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1680-
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1681-
; ALL-NEXT: ret i32 [[O2]]
1684+
; LE-LABEL: @loadCombine_4consecutive_mixsize2(
1685+
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
1686+
; LE-NEXT: ret i32 [[L1]]
1687+
;
1688+
; BE-LABEL: @loadCombine_4consecutive_mixsize2(
1689+
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1690+
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
1691+
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1692+
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1693+
; BE-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
1694+
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1695+
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
1696+
; BE-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i32
1697+
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1698+
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
1699+
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1700+
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1701+
; BE-NEXT: ret i32 [[O2]]
16821702
;
16831703
%p1 = getelementptr i8, ptr %p, i32 1
16841704
%p2 = getelementptr i8, ptr %p, i32 2
@@ -1699,20 +1719,24 @@ define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
16991719
}
17001720

17011721
define i32 @loadCombine_4consecutive_mixsize3(ptr %p) {
1702-
; ALL-LABEL: @loadCombine_4consecutive_mixsize3(
1703-
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1704-
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1705-
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1706-
; ALL-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 2
1707-
; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1708-
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1709-
; ALL-NEXT: [[E2:%.*]] = zext i16 [[L2]] to i32
1710-
; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1711-
; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1712-
; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1713-
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1714-
; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1715-
; ALL-NEXT: ret i32 [[O2]]
1722+
; LE-LABEL: @loadCombine_4consecutive_mixsize3(
1723+
; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
1724+
; LE-NEXT: ret i32 [[L1]]
1725+
;
1726+
; BE-LABEL: @loadCombine_4consecutive_mixsize3(
1727+
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
1728+
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
1729+
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1730+
; BE-NEXT: [[L2:%.*]] = load i16, ptr [[P1]], align 2
1731+
; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
1732+
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
1733+
; BE-NEXT: [[E2:%.*]] = zext i16 [[L2]] to i32
1734+
; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
1735+
; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
1736+
; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
1737+
; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
1738+
; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
1739+
; BE-NEXT: ret i32 [[O2]]
17161740
;
17171741
%p1 = getelementptr i8, ptr %p, i32 1
17181742
%p2 = getelementptr i8, ptr %p, i32 3
@@ -1767,25 +1791,29 @@ define i16 @loadCombine_mixsize_4bit(ptr %p) {
17671791
}
17681792

17691793
define i64 @loadCombine_8consecutive_mixsize(ptr %p) {
1770-
; ALL-LABEL: @loadCombine_8consecutive_mixsize(
1771-
; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
1772-
; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2
1773-
; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
1774-
; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1775-
; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1776-
; ALL-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
1777-
; ALL-NEXT: [[L4:%.*]] = load i32, ptr [[P3]], align 4
1778-
; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i64
1779-
; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i64
1780-
; ALL-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i64
1781-
; ALL-NEXT: [[E4:%.*]] = zext i32 [[L4]] to i64
1782-
; ALL-NEXT: [[S2:%.*]] = shl i64 [[E2]], 8
1783-
; ALL-NEXT: [[S3:%.*]] = shl i64 [[E3]], 16
1784-
; ALL-NEXT: [[S4:%.*]] = shl i64 [[E4]], 32
1785-
; ALL-NEXT: [[O1:%.*]] = or i64 [[E1]], [[S2]]
1786-
; ALL-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S3]]
1787-
; ALL-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S4]]
1788-
; ALL-NEXT: ret i64 [[O3]]
1794+
; LE-LABEL: @loadCombine_8consecutive_mixsize(
1795+
; LE-NEXT: [[L1:%.*]] = load i64, ptr [[P:%.*]], align 1
1796+
; LE-NEXT: ret i64 [[L1]]
1797+
;
1798+
; BE-LABEL: @loadCombine_8consecutive_mixsize(
1799+
; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1
1800+
; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2
1801+
; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 4
1802+
; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
1803+
; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
1804+
; BE-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
1805+
; BE-NEXT: [[L4:%.*]] = load i32, ptr [[P3]], align 4
1806+
; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i64
1807+
; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i64
1808+
; BE-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i64
1809+
; BE-NEXT: [[E4:%.*]] = zext i32 [[L4]] to i64
1810+
; BE-NEXT: [[S2:%.*]] = shl i64 [[E2]], 8
1811+
; BE-NEXT: [[S3:%.*]] = shl i64 [[E3]], 16
1812+
; BE-NEXT: [[S4:%.*]] = shl i64 [[E4]], 32
1813+
; BE-NEXT: [[O1:%.*]] = or i64 [[E1]], [[S2]]
1814+
; BE-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S3]]
1815+
; BE-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S4]]
1816+
; BE-NEXT: ret i64 [[O3]]
17891817
;
17901818
%p1 = getelementptr i8, ptr %p, i64 1
17911819
%p2 = getelementptr i8, ptr %p, i64 2

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