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[RISCV] Handle fixed-length vectors
1 parent 3a59255 commit 174e59e

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6 files changed

+698
-665
lines changed

6 files changed

+698
-665
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 23 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17364,6 +17364,9 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1736417364
case ISD::ZERO_EXTEND:
1736517365
Opcode = RISCVISD::VWMULU_VL;
1736617366
break;
17367+
// TODO:
17368+
// case RISCVISD::VSEXT_VL:
17369+
// case RISCVISD::VZEXT_VL:
1736717370
default:
1736817371
return SDValue();
1736917372
}
@@ -17386,23 +17389,30 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1738617389
return SDValue();
1738717390

1738817391
SDValue NarrowOp = LHS.getOperand(0);
17389-
uint64_t NarrowBits = NarrowOp.getSimpleValueType().getScalarSizeInBits();
17392+
MVT NarrowVT = NarrowOp.getSimpleValueType();
17393+
uint64_t NarrowBits = NarrowVT.getScalarSizeInBits();
1739017394
if (ShAmtInt >= NarrowBits)
1739117395
return SDValue();
17392-
EVT VT = N->getValueType(0);
17396+
MVT VT = N->getSimpleValueType(0);
1739317397
if (NarrowBits * 2 != VT.getScalarSizeInBits())
1739417398
return SDValue();
1739517399

1739617400
SelectionDAG &DAG = DCI.DAG;
17401+
MVT NarrowContainerVT = NarrowVT;
17402+
MVT ContainerVT = VT;
1739717403
SDLoc DL(N);
1739817404
SDValue Passthru, Mask, VL;
1739917405
switch (N->getOpcode()) {
1740017406
case ISD::SHL:
17401-
if (!VT.isScalableVector())
17402-
return SDValue(); // TODO: handle fixed length vectors
17407+
if (VT.isFixedLengthVector()) {
17408+
NarrowContainerVT =
17409+
getContainerForFixedLengthVector(DAG, NarrowVT, Subtarget);
17410+
NarrowOp =
17411+
convertToScalableVector(NarrowContainerVT, NarrowOp, DAG, Subtarget);
17412+
ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
17413+
}
1740317414
Passthru = DAG.getUNDEF(VT);
17404-
std::tie(Mask, VL) =
17405-
getDefaultScalableVLOps(VT.getSimpleVT(), DL, DAG, Subtarget);
17415+
std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
1740617416
break;
1740717417
case RISCVISD::SHL_VL:
1740817418
Passthru = N->getOperand(2);
@@ -17412,10 +17422,13 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1741217422
default:
1741317423
llvm_unreachable("Expected SHL");
1741417424
}
17415-
return DAG.getNode(
17416-
Opcode, DL, VT, NarrowOp,
17417-
DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowOp.getValueType()),
17418-
Passthru, Mask, VL);
17425+
SDValue Mul =
17426+
DAG.getNode(Opcode, DL, ContainerVT, NarrowOp,
17427+
DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), ContainerVT),
17428+
Passthru, Mask, VL);
17429+
if (VT.isFixedLengthVector())
17430+
return convertFromScalableVector(VT, Mul, DAG, Subtarget);
17431+
return Mul;
1741917432
}
1742017433

1742117434
SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,

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