Addresses shortcomings, add more tests

Author: badumbatish

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -19,6 +19,7 @@
 #include "WebAssemblyTargetMachine.h"
 #include "WebAssemblyUtilities.h"
 #include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
@@ -3394,7 +3395,13 @@ combineVectorSizedSetCCEquality(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   EVT OpVT = X.getValueType();
 
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+  if (!isIntEqualitySetCC(CC))
+    return SDValue();
+
   SelectionDAG &DAG = DCI.DAG;
+  if (DCI.DAG.getMachineFunction().getFunction().hasFnAttribute(
+          Attribute::NoImplicitFloat))
+    return SDValue();
   // We're looking for an oversized integer equality comparison.
   if (!OpVT.isScalarInteger() || !OpVT.isByteSized() || OpVT != MVT::i128 ||
       !Subtarget->hasSIMD128())
@@ -3413,7 +3420,6 @@ combineVectorSizedSetCCEquality(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
 
   SDValue VecX = DAG.getBitcast(VecVT, X);
   SDValue VecY = DAG.getBitcast(VecVT, Y);
-
   SDValue Cmp = DAG.getSetCC(DL, VecVT, VecX, VecY, CC);
 
   SDValue AllTrue = DAG.getNode(

llvm/test/CodeGen/WebAssembly/memcmp-expand.ll

@@ -127,7 +127,6 @@ define i1 @memcmp_expand_8(ptr %a, ptr %b) {
   ret i1 %res
 }
 
-; TODO: Should be using a single load i64x2 or equivalent in bitsizes
 define i1 @memcmp_expand_16(ptr %a, ptr %b) {
 ; CHECK-LABEL: memcmp_expand_16:
 ; CHECK:         .functype memcmp_expand_16 (i32, i32) -> (i32)

llvm/test/CodeGen/WebAssembly/simd-setcc.ll

@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s  -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
+
+target triple = "wasm32-unknown-unknown"
+
+declare i32 @memcmp(ptr, ptr, i32)
+
+define i1 @setcc_load(ptr %a, ptr %b) {
+; CHECK-LABEL: setcc_load:
+; CHECK:         .functype setcc_load (i32, i32) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    v128.load $push1=, 0($0):p2align=0
+; CHECK-NEXT:    v128.load $push0=, 0($1):p2align=0
+; CHECK-NEXT:    i8x16.eq $push2=, $pop1, $pop0
+; CHECK-NEXT:    i8x16.all_true $push3=, $pop2
+; CHECK-NEXT:    i32.eqz $push4=, $pop3
+; CHECK-NEXT:    return $pop4
+  %cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
+  %res = icmp eq i32 %cmp_16, 0
+  ret i1 %res
+}
+
+; INFO: Negative test: noimplicitfloat disables simd
+define i1 @setcc_load_should_not_vectorize(ptr %a, ptr %b) noimplicitfloat {
+; CHECK-LABEL: setcc_load_should_not_vectorize:
+; CHECK:         .functype setcc_load_should_not_vectorize (i32, i32) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    i64.load $push4=, 0($0):p2align=0
+; CHECK-NEXT:    i64.load $push3=, 0($1):p2align=0
+; CHECK-NEXT:    i64.xor $push5=, $pop4, $pop3
+; CHECK-NEXT:    i64.load $push1=, 8($0):p2align=0
+; CHECK-NEXT:    i64.load $push0=, 8($1):p2align=0
+; CHECK-NEXT:    i64.xor $push2=, $pop1, $pop0
+; CHECK-NEXT:    i64.or $push6=, $pop5, $pop2
+; CHECK-NEXT:    i64.eqz $push7=, $pop6
+; CHECK-NEXT:    return $pop7
+  %cmp_16 = call i32 @memcmp(ptr %a, ptr %b, i32 16)
+  %res = icmp eq i32 %cmp_16, 0
+  ret i1 %res
+}
+
+define i1 @setcc_eq_const_i128(ptr %ptr) {
+; CHECK-LABEL: setcc_eq_const_i128:
+; CHECK:         .functype setcc_eq_const_i128 (i32) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    v128.load $push0=, 0($0)
+; CHECK-NEXT:    v128.const $push1=, 6, 0
+; CHECK-NEXT:    i8x16.eq $push2=, $pop0, $pop1
+; CHECK-NEXT:    i8x16.all_true $push3=, $pop2
+; CHECK-NEXT:    i32.eqz $push4=, $pop3
+; CHECK-NEXT:    return $pop4
+  %l = load i128, ptr %ptr
+  %res = icmp eq i128 %l, 6
+  ret i1 %res
+}
+
+define i1 @setcc_ne_const_i128(ptr %ptr) {
+; CHECK-LABEL: setcc_ne_const_i128:
+; CHECK:         .functype setcc_ne_const_i128 (i32) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    v128.load $push0=, 0($0)
+; CHECK-NEXT:    v128.const $push1=, 16, 0
+; CHECK-NEXT:    i8x16.ne $push2=, $pop0, $pop1
+; CHECK-NEXT:    i8x16.all_true $push3=, $pop2
+; CHECK-NEXT:    return $pop3
+  %l = load i128, ptr %ptr
+  %res = icmp ne i128 %l, 16
+  ret i1 %res
+}
+
+; INFO: Negative test: only eq and ne works
+define i1 @setcc_slt_const_i128(ptr %ptr) {
+; CHECK-LABEL: setcc_slt_const_i128:
+; CHECK:         .functype setcc_slt_const_i128 (i32) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    i64.load $push2=, 0($0)
+; CHECK-NEXT:    i64.const $push3=, 25
+; CHECK-NEXT:    i64.lt_u $push4=, $pop2, $pop3
+; CHECK-NEXT:    i64.load $push8=, 8($0)
+; CHECK-NEXT:    local.tee $push7=, $1=, $pop8
+; CHECK-NEXT:    i64.const $push0=, 0
+; CHECK-NEXT:    i64.lt_s $push1=, $pop7, $pop0
+; CHECK-NEXT:    i64.eqz $push5=, $1
+; CHECK-NEXT:    i32.select $push6=, $pop4, $pop1, $pop5
+; CHECK-NEXT:    return $pop6
+  %l = load i128, ptr %ptr
+  %res = icmp slt i128 %l, 25
+  ret i1 %res
+}