Rename VecTernaryOp operands to mirror AST representation

Author: AmrDeveloper

clang/include/clang/CIR/Dialect/IR/CIROps.td

@@ -2199,7 +2199,7 @@ def VecShuffleDynamicOp : CIR_Op<"vec.shuffle.dynamic",
 //===----------------------------------------------------------------------===//
 
 def VecTernaryOp : CIR_Op<"vec.ternary",
-                   [Pure, AllTypesMatch<["result", "vec1", "vec2"]>]> {
+                   [Pure, AllTypesMatch<["result", "lhs", "rhs"]>]> {
   let summary = "The `cond ? a : b` ternary operator for vector types";
   let description = [{
     The `cir.vec.ternary` operation represents the C/C++ ternary operator,
@@ -2218,14 +2218,14 @@ def VecTernaryOp : CIR_Op<"vec.ternary",
 
   let arguments = (ins
     CIR_VectorOfIntType:$cond,
-    CIR_VectorType:$vec1,
-    CIR_VectorType:$vec2
+    CIR_VectorType:$lhs,
+    CIR_VectorType:$rhs
   );
 
   let results = (outs CIR_VectorType:$result);
   let assemblyFormat = [{
-    `(` $cond `,` $vec1 `,` $vec2 `)` `:` qualified(type($cond)) `,`
-    qualified(type($vec1)) attr-dict
+    `(` $cond `,` $lhs`,` $rhs `)` `:` qualified(type($cond)) `,`
+    qualified(type($lhs)) attr-dict
   }];
   let hasVerifier = 1;
 }

clang/lib/CIR/Dialect/IR/CIRDialect.cpp

@@ -1598,10 +1598,10 @@ LogicalResult cir::VecTernaryOp::verify() {
   // other operands.  (The automatic verification already checked that all
   // operands are vector types and that the second and third operands are the
   // same type.)
-  if (getCond().getType().getSize() != getVec1().getType().getSize()) {
+  if (getCond().getType().getSize() != getLhs().getType().getSize()) {
     return emitOpError() << ": the number of elements in "
-                         << getCond().getType() << " and "
-                         << getVec1().getType() << " don't match";
+                         << getCond().getType() << " and " << getLhs().getType()
+                         << " don't match";
   }
   return success();
 }

clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

@@ -1945,7 +1945,7 @@ mlir::LogicalResult CIRToLLVMVecTernaryOpLowering::matchAndRewrite(
           op.getCond().getLoc(),
           typeConverter->convertType(op.getCond().getType())));
   rewriter.replaceOpWithNewOp<mlir::LLVM::SelectOp>(
-      op, bitVec, adaptor.getVec1(), adaptor.getVec2());
+      op, bitVec, adaptor.getLhs(), adaptor.getRhs());
   return mlir::success();
 }