fixup! clang format

hchandel · hchandel · commit 1a443e589dbd · 2025-09-09T14:54:13.000+05:30
Change-Id: If3ff9fb4bdcfd557426f863b5235d2f10535d00b
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -677,7 +677,6 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
   return false;
 }
 
-
 bool RISCVDAGToDAGISel::trySignedBitfieldInsertInSign(SDNode *Node) {
   // Only supported with XAndesPerf at the moment.
   if (!Subtarget->hasVendorXAndesPerf())

Original file line number	Diff line number	Diff line change
`@@ -677,7 +677,6 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {`
`677`	`677`	`return false;`
`678`	`678`	`}`
`679`	`679`
`680`		`-`
`681`	`680`	`bool RISCVDAGToDAGISel::trySignedBitfieldInsertInSign(SDNode *Node) {`
`682`	`681`	`// Only supported with XAndesPerf at the moment.`
`683`	`682`	`if (!Subtarget->hasVendorXAndesPerf())`