Update tests

Signed-off-by: John Lu <[email protected]>

Author: LU-JOHN

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -5956,10 +5956,6 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_XOR_B64);
   case AMDGPU::S_UADDO_PSEUDO:
   case AMDGPU::S_USUBO_PSEUDO: {
-<<<<<<< HEAD
-=======
-    const DebugLoc &DL = MI.getDebugLoc();
->>>>>>> 27321ddcdbe2 (Clean up code.)
     MachineOperand &Dest0 = MI.getOperand(0);
     MachineOperand &Dest1 = MI.getOperand(1);
     MachineOperand &Src0 = MI.getOperand(2);

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

@@ -2215,11 +2215,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; VI-NEXT:    s_add_i32 s14, s8, s9
 ; VI-NEXT:    s_sub_i32 s10, s3, s14
 ; VI-NEXT:    v_readfirstlane_b32 s8, v0
-; VI-NEXT:    s_sub_i32 s15, s2, s8
+; VI-NEXT:    s_sub_u32 s15, s2, s8
 ; VI-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; VI-NEXT:    s_cmp_lg_u64 s[8:9], 0
 ; VI-NEXT:    s_subb_u32 s16, s10, s5
-; VI-NEXT:    s_sub_i32 s17, s15, s4
+; VI-NEXT:    s_sub_u32 s17, s15, s4
 ; VI-NEXT:    s_cselect_b64 s[10:11], 1, 0
 ; VI-NEXT:    s_cmp_lg_u64 s[10:11], 0
 ; VI-NEXT:    s_subb_u32 s10, s16, 0
@@ -2329,7 +2329,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX9-NEXT:    s_mul_i32 s9, s12, s9
 ; GFX9-NEXT:    s_add_u32 s9, s13, s9
 ; GFX9-NEXT:    s_addc_u32 s13, 0, s14
-; GFX9-NEXT:    s_add_i32 s14, s8, s9
+; GFX9-NEXT:    s_add_u32 s14, s8, s9
 ; GFX9-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; GFX9-NEXT:    s_cmp_lg_u64 s[8:9], 0
 ; GFX9-NEXT:    s_addc_u32 s12, s12, s13
@@ -2353,21 +2353,21 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX9-NEXT:    s_mul_i32 s8, s12, s8
 ; GFX9-NEXT:    s_add_u32 s8, s10, s8
 ; GFX9-NEXT:    s_addc_u32 s10, 0, s9
-; GFX9-NEXT:    s_add_i32 s14, s14, s8
+; GFX9-NEXT:    s_add_u32 s11, s14, s8
 ; GFX9-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; GFX9-NEXT:    s_cmp_lg_u64 s[8:9], 0
 ; GFX9-NEXT:    s_addc_u32 s8, s12, s10
 ; GFX9-NEXT:    s_mul_i32 s10, s2, s8
-; GFX9-NEXT:    s_mul_hi_u32 s11, s2, s14
+; GFX9-NEXT:    s_mul_hi_u32 s12, s2, s11
 ; GFX9-NEXT:    s_mul_hi_u32 s9, s2, s8
-; GFX9-NEXT:    s_add_u32 s10, s11, s10
+; GFX9-NEXT:    s_add_u32 s10, s12, s10
 ; GFX9-NEXT:    s_addc_u32 s9, 0, s9
-; GFX9-NEXT:    s_mul_i32 s13, s3, s14
-; GFX9-NEXT:    s_mul_hi_u32 s12, s3, s14
-; GFX9-NEXT:    s_add_u32 s10, s10, s13
-; GFX9-NEXT:    s_mul_hi_u32 s11, s3, s8
-; GFX9-NEXT:    s_addc_u32 s9, s9, s12
-; GFX9-NEXT:    s_addc_u32 s10, s11, 0
+; GFX9-NEXT:    s_mul_hi_u32 s13, s3, s11
+; GFX9-NEXT:    s_mul_i32 s11, s3, s11
+; GFX9-NEXT:    s_add_u32 s10, s10, s11
+; GFX9-NEXT:    s_mul_hi_u32 s12, s3, s8
+; GFX9-NEXT:    s_addc_u32 s9, s9, s13
+; GFX9-NEXT:    s_addc_u32 s10, s12, 0
 ; GFX9-NEXT:    s_mul_i32 s8, s3, s8
 ; GFX9-NEXT:    s_add_u32 s12, s9, s8
 ; GFX9-NEXT:    s_addc_u32 s13, 0, s10
@@ -2378,11 +2378,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX9-NEXT:    s_add_i32 s14, s8, s9
 ; GFX9-NEXT:    s_sub_i32 s10, s3, s14
 ; GFX9-NEXT:    s_mul_i32 s8, s6, s12
-; GFX9-NEXT:    s_sub_i32 s15, s2, s8
+; GFX9-NEXT:    s_sub_u32 s15, s2, s8
 ; GFX9-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; GFX9-NEXT:    s_cmp_lg_u64 s[8:9], 0
 ; GFX9-NEXT:    s_subb_u32 s16, s10, s7
-; GFX9-NEXT:    s_sub_i32 s17, s15, s6
+; GFX9-NEXT:    s_sub_u32 s17, s15, s6
 ; GFX9-NEXT:    s_cselect_b64 s[10:11], 1, 0
 ; GFX9-NEXT:    s_cmp_lg_u64 s[10:11], 0
 ; GFX9-NEXT:    s_subb_u32 s10, s16, 0
@@ -2488,7 +2488,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1010-NEXT:    s_addc_u32 s13, s17, 0
 ; GFX1010-NEXT:    s_add_u32 s11, s12, s11
 ; GFX1010-NEXT:    s_addc_u32 s12, 0, s13
-; GFX1010-NEXT:    s_add_i32 s8, s8, s11
+; GFX1010-NEXT:    s_add_u32 s8, s8, s11
 ; GFX1010-NEXT:    s_cselect_b32 s11, 1, 0
 ; GFX1010-NEXT:    s_mul_hi_u32 s13, s9, s8
 ; GFX1010-NEXT:    s_cmp_lg_u32 s11, 0
@@ -2512,7 +2512,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1010-NEXT:    s_addc_u32 s11, s11, 0
 ; GFX1010-NEXT:    s_add_u32 s9, s10, s9
 ; GFX1010-NEXT:    s_addc_u32 s10, 0, s11
-; GFX1010-NEXT:    s_add_i32 s8, s8, s9
+; GFX1010-NEXT:    s_add_u32 s8, s8, s9
 ; GFX1010-NEXT:    s_cselect_b32 s9, 1, 0
 ; GFX1010-NEXT:    s_mul_hi_u32 s11, s2, s8
 ; GFX1010-NEXT:    s_cmp_lg_u32 s9, 0
@@ -2537,11 +2537,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1010-NEXT:    s_mul_i32 s10, s6, s5
 ; GFX1010-NEXT:    s_add_i32 s9, s9, s11
 ; GFX1010-NEXT:    s_sub_i32 s11, s3, s9
-; GFX1010-NEXT:    s_sub_i32 s10, s2, s10
+; GFX1010-NEXT:    s_sub_u32 s10, s2, s10
 ; GFX1010-NEXT:    s_cselect_b32 s12, 1, 0
 ; GFX1010-NEXT:    s_cmp_lg_u32 s12, 0
 ; GFX1010-NEXT:    s_subb_u32 s11, s11, s7
-; GFX1010-NEXT:    s_sub_i32 s13, s10, s6
+; GFX1010-NEXT:    s_sub_u32 s13, s10, s6
 ; GFX1010-NEXT:    s_cselect_b32 s14, 1, 0
 ; GFX1010-NEXT:    s_cmp_lg_u32 s14, 0
 ; GFX1010-NEXT:    s_subb_u32 s11, s11, 0
@@ -2648,7 +2648,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1030W32-NEXT:    s_addc_u32 s13, s17, 0
 ; GFX1030W32-NEXT:    s_add_u32 s11, s12, s11
 ; GFX1030W32-NEXT:    s_addc_u32 s12, 0, s13
-; GFX1030W32-NEXT:    s_add_i32 s8, s8, s11
+; GFX1030W32-NEXT:    s_add_u32 s8, s8, s11
 ; GFX1030W32-NEXT:    s_cselect_b32 s11, 1, 0
 ; GFX1030W32-NEXT:    s_mul_hi_u32 s13, s9, s8
 ; GFX1030W32-NEXT:    s_cmp_lg_u32 s11, 0
@@ -2672,7 +2672,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1030W32-NEXT:    s_addc_u32 s11, s11, 0
 ; GFX1030W32-NEXT:    s_add_u32 s9, s10, s9
 ; GFX1030W32-NEXT:    s_addc_u32 s10, 0, s11
-; GFX1030W32-NEXT:    s_add_i32 s8, s8, s9
+; GFX1030W32-NEXT:    s_add_u32 s8, s8, s9
 ; GFX1030W32-NEXT:    s_cselect_b32 s9, 1, 0
 ; GFX1030W32-NEXT:    s_mul_hi_u32 s11, s2, s8
 ; GFX1030W32-NEXT:    s_cmp_lg_u32 s9, 0
@@ -2697,11 +2697,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1030W32-NEXT:    s_mul_i32 s10, s4, s7
 ; GFX1030W32-NEXT:    s_add_i32 s9, s9, s11
 ; GFX1030W32-NEXT:    s_sub_i32 s11, s3, s9
-; GFX1030W32-NEXT:    s_sub_i32 s10, s2, s10
+; GFX1030W32-NEXT:    s_sub_u32 s10, s2, s10
 ; GFX1030W32-NEXT:    s_cselect_b32 s12, 1, 0
 ; GFX1030W32-NEXT:    s_cmp_lg_u32 s12, 0
 ; GFX1030W32-NEXT:    s_subb_u32 s11, s11, s5
-; GFX1030W32-NEXT:    s_sub_i32 s13, s10, s4
+; GFX1030W32-NEXT:    s_sub_u32 s13, s10, s4
 ; GFX1030W32-NEXT:    s_cselect_b32 s14, 1, 0
 ; GFX1030W32-NEXT:    s_cmp_lg_u32 s14, 0
 ; GFX1030W32-NEXT:    s_subb_u32 s11, s11, 0
@@ -2808,7 +2808,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1030W64-NEXT:    s_addc_u32 s12, s16, 0
 ; GFX1030W64-NEXT:    s_add_u32 s7, s11, s7
 ; GFX1030W64-NEXT:    s_addc_u32 s11, 0, s12
-; GFX1030W64-NEXT:    s_add_i32 s12, s6, s7
+; GFX1030W64-NEXT:    s_add_u32 s12, s6, s7
 ; GFX1030W64-NEXT:    s_cselect_b64 s[6:7], 1, 0
 ; GFX1030W64-NEXT:    s_mul_hi_u32 s13, s9, s12
 ; GFX1030W64-NEXT:    s_cmp_lg_u64 s[6:7], 0
@@ -2832,16 +2832,16 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1030W64-NEXT:    s_addc_u32 s7, s10, 0
 ; GFX1030W64-NEXT:    s_add_u32 s6, s6, s9
 ; GFX1030W64-NEXT:    s_addc_u32 s9, 0, s7
-; GFX1030W64-NEXT:    s_add_i32 s12, s12, s6
+; GFX1030W64-NEXT:    s_add_u32 s10, s12, s6
 ; GFX1030W64-NEXT:    s_cselect_b64 s[6:7], 1, 0
-; GFX1030W64-NEXT:    s_mul_hi_u32 s10, s2, s12
+; GFX1030W64-NEXT:    s_mul_hi_u32 s11, s2, s10
 ; GFX1030W64-NEXT:    s_cmp_lg_u64 s[6:7], 0
-; GFX1030W64-NEXT:    s_mul_hi_u32 s6, s3, s12
+; GFX1030W64-NEXT:    s_mul_hi_u32 s6, s3, s10
 ; GFX1030W64-NEXT:    s_addc_u32 s7, s8, s9
-; GFX1030W64-NEXT:    s_mul_i32 s8, s3, s12
-; GFX1030W64-NEXT:    s_mul_i32 s11, s2, s7
+; GFX1030W64-NEXT:    s_mul_i32 s8, s3, s10
+; GFX1030W64-NEXT:    s_mul_i32 s10, s2, s7
 ; GFX1030W64-NEXT:    s_mul_hi_u32 s9, s2, s7
-; GFX1030W64-NEXT:    s_add_u32 s10, s10, s11
+; GFX1030W64-NEXT:    s_add_u32 s10, s11, s10
 ; GFX1030W64-NEXT:    s_addc_u32 s9, 0, s9
 ; GFX1030W64-NEXT:    s_mul_hi_u32 s12, s3, s7
 ; GFX1030W64-NEXT:    s_add_u32 s8, s10, s8
@@ -2857,11 +2857,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1030W64-NEXT:    s_add_i32 s12, s6, s8
 ; GFX1030W64-NEXT:    s_mul_i32 s6, s4, s10
 ; GFX1030W64-NEXT:    s_sub_i32 s8, s3, s12
-; GFX1030W64-NEXT:    s_sub_i32 s13, s2, s6
+; GFX1030W64-NEXT:    s_sub_u32 s13, s2, s6
 ; GFX1030W64-NEXT:    s_cselect_b64 s[6:7], 1, 0
 ; GFX1030W64-NEXT:    s_cmp_lg_u64 s[6:7], 0
 ; GFX1030W64-NEXT:    s_subb_u32 s14, s8, s5
-; GFX1030W64-NEXT:    s_sub_i32 s15, s13, s4
+; GFX1030W64-NEXT:    s_sub_u32 s15, s13, s4
 ; GFX1030W64-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; GFX1030W64-NEXT:    s_cmp_lg_u64 s[8:9], 0
 ; GFX1030W64-NEXT:    s_subb_u32 s8, s14, 0
@@ -2973,7 +2973,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX11-NEXT:    s_addc_u32 s13, s17, 0
 ; GFX11-NEXT:    s_add_u32 s11, s12, s11
 ; GFX11-NEXT:    s_addc_u32 s12, 0, s13
-; GFX11-NEXT:    s_add_i32 s8, s8, s11
+; GFX11-NEXT:    s_add_u32 s8, s8, s11
 ; GFX11-NEXT:    s_cselect_b32 s11, 1, 0
 ; GFX11-NEXT:    s_mul_hi_u32 s13, s9, s8
 ; GFX11-NEXT:    s_cmp_lg_u32 s11, 0
@@ -2997,7 +2997,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX11-NEXT:    s_addc_u32 s11, s11, 0
 ; GFX11-NEXT:    s_add_u32 s9, s10, s9
 ; GFX11-NEXT:    s_addc_u32 s10, 0, s11
-; GFX11-NEXT:    s_add_i32 s8, s8, s9
+; GFX11-NEXT:    s_add_u32 s8, s8, s9
 ; GFX11-NEXT:    s_cselect_b32 s9, 1, 0
 ; GFX11-NEXT:    s_mul_hi_u32 s11, s2, s8
 ; GFX11-NEXT:    s_cmp_lg_u32 s9, 0
@@ -3023,11 +3023,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX11-NEXT:    s_add_i32 s9, s9, s11
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_sub_i32 s11, s3, s9
-; GFX11-NEXT:    s_sub_i32 s10, s2, s10
+; GFX11-NEXT:    s_sub_u32 s10, s2, s10
 ; GFX11-NEXT:    s_cselect_b32 s12, 1, 0
 ; GFX11-NEXT:    s_cmp_lg_u32 s12, 0
 ; GFX11-NEXT:    s_subb_u32 s11, s11, s5
-; GFX11-NEXT:    s_sub_i32 s13, s10, s4
+; GFX11-NEXT:    s_sub_u32 s13, s10, s4
 ; GFX11-NEXT:    s_cselect_b32 s14, 1, 0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_cmp_lg_u32 s14, 0
@@ -3105,7 +3105,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
 ; GFX1250-NEXT:    s_or_b64 s[6:7], s[2:3], s[4:5]
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_and_b64 s[6:7], s[6:7], lit64(0xffffffff00000000)
+; GFX1250-NEXT:    s_and_b64 s[6:7], s[6:7], 0xffffffff00000000
 ; GFX1250-NEXT:    s_cmp_lg_u64 s[6:7], 0
 ; GFX1250-NEXT:    s_cbranch_scc0 .LBB16_4
 ; GFX1250-NEXT:  ; %bb.1:
@@ -3140,7 +3140,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1250-NEXT:    s_add_co_ci_u32 s13, s18, 0
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_add_nc_u64 s[12:13], s[6:7], s[12:13]
-; GFX1250-NEXT:    s_add_co_i32 s8, s8, s12
+; GFX1250-NEXT:    s_add_co_u32 s8, s8, s12
 ; GFX1250-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_cmp_lg_u32 s6, 0
@@ -3160,7 +3160,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1250-NEXT:    s_add_co_ci_u32 s11, s16, 0
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_add_nc_u64 s[10:11], s[6:7], s[10:11]
-; GFX1250-NEXT:    s_add_co_i32 s8, s8, s10
+; GFX1250-NEXT:    s_add_co_u32 s8, s8, s10
 ; GFX1250-NEXT:    s_cselect_b32 s10, 1, 0
 ; GFX1250-NEXT:    s_mul_hi_u32 s6, s2, s8
 ; GFX1250-NEXT:    s_cmp_lg_u32 s10, 0
@@ -3177,17 +3177,17 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GFX1250-NEXT:    s_add_co_ci_u32 s11, s13, 0
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_add_nc_u64 s[8:9], s[6:7], s[10:11]
-; GFX1250-NEXT:    s_and_b64 s[10:11], s[8:9], lit64(0xffffffff00000000)
+; GFX1250-NEXT:    s_and_b64 s[10:11], s[8:9], 0xffffffff00000000
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_or_b32 s10, s10, s8
 ; GFX1250-NEXT:    s_mul_u64 s[8:9], s[4:5], s[10:11]
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_sub_co_i32 s6, s2, s8
+; GFX1250-NEXT:    s_sub_co_u32 s6, s2, s8
 ; GFX1250-NEXT:    s_cselect_b32 s8, 1, 0
 ; GFX1250-NEXT:    s_sub_co_i32 s12, s3, s9
 ; GFX1250-NEXT:    s_cmp_lg_u32 s8, 0
 ; GFX1250-NEXT:    s_sub_co_ci_u32 s12, s12, s5
-; GFX1250-NEXT:    s_sub_co_i32 s13, s6, s4
+; GFX1250-NEXT:    s_sub_co_u32 s13, s6, s4
 ; GFX1250-NEXT:    s_cselect_b32 s14, 1, 0
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_cmp_lg_u32 s14, 0

llvm/test/CodeGen/AMDGPU/carryout-selection.ll

@@ -11,7 +11,7 @@ define i32 @s_add_co_select_user() {
 ; GFX7-NEXT:    s_mov_b64 s[4:5], 0
 ; GFX7-NEXT:    s_load_dword s6, s[4:5], 0x0
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-NEXT:    s_add_i32 s7, s6, s6
+; GFX7-NEXT:    s_add_u32 s7, s6, s6
 ; GFX7-NEXT:    s_cselect_b64 s[4:5], 1, 0
 ; GFX7-NEXT:    s_or_b32 s4, s4, s5
 ; GFX7-NEXT:    s_cmp_lg_u32 s4, 0
@@ -30,7 +30,7 @@ define i32 @s_add_co_select_user() {
 ; GFX9-NEXT:    s_mov_b64 s[4:5], 0
 ; GFX9-NEXT:    s_load_dword s6, s[4:5], 0x0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_add_i32 s7, s6, s6
+; GFX9-NEXT:    s_add_u32 s7, s6, s6
 ; GFX9-NEXT:    s_cselect_b64 s[4:5], 1, 0
 ; GFX9-NEXT:    s_cmp_lg_u64 s[4:5], 0
 ; GFX9-NEXT:    s_addc_u32 s8, s6, 0
@@ -48,7 +48,7 @@ define i32 @s_add_co_select_user() {
 ; GFX10-NEXT:    s_mov_b64 s[4:5], 0
 ; GFX10-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    s_add_i32 s5, s4, s4
+; GFX10-NEXT:    s_add_u32 s5, s4, s4
 ; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX10-NEXT:    s_cmp_lg_u32 s6, 0
 ; GFX10-NEXT:    s_addc_u32 s6, s4, 0
@@ -66,7 +66,7 @@ define i32 @s_add_co_select_user() {
 ; GFX11-NEXT:    s_mov_b64 s[0:1], 0
 ; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_add_i32 s1, s0, s0
+; GFX11-NEXT:    s_add_u32 s1, s0, s0
 ; GFX11-NEXT:    s_cselect_b32 s2, 1, 0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_cmp_lg_u32 s2, 0

llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll

@@ -11,7 +11,7 @@
 define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0) {
 ; CHECK-LABEL: s_uaddo_pseudo:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_add_i32 s0, s0, 1
+; CHECK-NEXT:    s_add_u32 s0, s0, 1
 ; CHECK-NEXT:    s_cselect_b64 s[0:1], 1, 0
 ; CHECK-NEXT:    s_cmp_lg_u64 s[0:1], 0
 ; CHECK-NEXT:    s_addc_u32 s0, 1, 0

llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll

@@ -54,7 +54,7 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GCN-NEXT:    s_mul_i32 s1, s14, s1
 ; GCN-NEXT:    s_add_u32 s1, s15, s1
 ; GCN-NEXT:    s_addc_u32 s15, 0, s16
-; GCN-NEXT:    s_add_i32 s16, s0, s1
+; GCN-NEXT:    s_add_u32 s16, s0, s1
 ; GCN-NEXT:    v_mov_b32_e32 v0, s16
 ; GCN-NEXT:    s_cselect_b64 s[0:1], 1, 0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s12, v0
@@ -87,7 +87,7 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GCN-NEXT:    s_mul_i32 s0, s14, s0
 ; GCN-NEXT:    s_add_u32 s0, s1, s0
 ; GCN-NEXT:    s_addc_u32 s12, 0, s12
-; GCN-NEXT:    s_add_i32 s15, s16, s0
+; GCN-NEXT:    s_add_u32 s15, s16, s0
 ; GCN-NEXT:    s_cselect_b64 s[0:1], 1, 0
 ; GCN-NEXT:    s_or_b32 s0, s0, s1
 ; GCN-NEXT:    s_cmp_lg_u32 s0, 0
@@ -128,12 +128,12 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) {
 ; GCN-NEXT:    s_add_i32 s16, s4, s5
 ; GCN-NEXT:    s_sub_i32 s17, s7, s16
 ; GCN-NEXT:    s_mul_i32 s4, s10, s14
-; GCN-NEXT:    s_sub_i32 s6, s6, s4
+; GCN-NEXT:    s_sub_u32 s6, s6, s4
 ; GCN-NEXT:    s_cselect_b64 s[4:5], 1, 0
 ; GCN-NEXT:    s_or_b32 s18, s4, s5
 ; GCN-NEXT:    s_cmp_lg_u32 s18, 0
 ; GCN-NEXT:    s_subb_u32 s17, s17, s11
-; GCN-NEXT:    s_sub_i32 s19, s6, s10
+; GCN-NEXT:    s_sub_u32 s19, s6, s10
 ; GCN-NEXT:    s_cselect_b64 s[4:5], 1, 0
 ; GCN-NEXT:    s_or_b32 s4, s4, s5
 ; GCN-NEXT:    s_cmp_lg_u32 s4, 0
@@ -1190,7 +1190,7 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
 ; GCN-NEXT:    s_mul_i32 s9, s11, s9
 ; GCN-NEXT:    s_add_u32 s9, s12, s9
 ; GCN-NEXT:    s_addc_u32 s12, 0, s13
-; GCN-NEXT:    s_add_i32 s13, s8, s9
+; GCN-NEXT:    s_add_u32 s13, s8, s9
 ; GCN-NEXT:    v_mov_b32_e32 v0, s13
 ; GCN-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s2, v0
@@ -1223,12 +1223,12 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
 ; GCN-NEXT:    s_mul_i32 s8, s11, s8
 ; GCN-NEXT:    s_add_u32 s2, s2, s8
 ; GCN-NEXT:    s_addc_u32 s10, 0, s9
-; GCN-NEXT:    s_add_i32 s13, s13, s2
+; GCN-NEXT:    s_add_u32 s2, s13, s2
 ; GCN-NEXT:    s_cselect_b64 s[8:9], 1, 0
-; GCN-NEXT:    s_or_b32 s2, s8, s9
-; GCN-NEXT:    s_cmp_lg_u32 s2, 0
+; GCN-NEXT:    s_or_b32 s8, s8, s9
+; GCN-NEXT:    s_cmp_lg_u32 s8, 0
 ; GCN-NEXT:    s_addc_u32 s8, s11, s10
-; GCN-NEXT:    v_mul_hi_u32 v1, s13, 24
+; GCN-NEXT:    v_mul_hi_u32 v1, s2, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, s8, 24
 ; GCN-NEXT:    s_mul_i32 s8, s8, 24
 ; GCN-NEXT:    s_mov_b32 s2, -1
@@ -1243,12 +1243,12 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x)
 ; GCN-NEXT:    s_add_i32 s11, s9, s8
 ; GCN-NEXT:    s_sub_i32 s12, 0, s11
 ; GCN-NEXT:    s_mul_i32 s8, s6, s10
-; GCN-NEXT:    s_sub_i32 s13, 24, s8
+; GCN-NEXT:    s_sub_u32 s13, 24, s8
 ; GCN-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; GCN-NEXT:    s_or_b32 s14, s8, s9
 ; GCN-NEXT:    s_cmp_lg_u32 s14, 0
 ; GCN-NEXT:    s_subb_u32 s12, s12, s7
-; GCN-NEXT:    s_sub_i32 s15, s13, s6
+; GCN-NEXT:    s_sub_u32 s15, s13, s6
 ; GCN-NEXT:    s_cselect_b64 s[8:9], 1, 0
 ; GCN-NEXT:    s_or_b32 s8, s8, s9
 ; GCN-NEXT:    s_cmp_lg_u32 s8, 0