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8 | 8 | ; GCN-ISEL: S_UADDO_PSEUDO
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9 | 9 | ; GCN-ISEL: S_ADD_CO_PSEUDO
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10 | 10 |
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11 |
| -define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0, i32 inreg %val1) { |
| 11 | +define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0) { |
12 | 12 | ; CHECK-LABEL: s_uaddo_pseudo:
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13 | 13 | ; CHECK: ; %bb.0:
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14 |
| -; CHECK-NEXT: s_add_i32 s0, s0, s1 |
| 14 | +; CHECK-NEXT: s_add_i32 s0, s0, 1 |
15 | 15 | ; CHECK-NEXT: s_cselect_b64 s[0:1], 1, 0
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16 | 16 | ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
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17 | 17 | ; CHECK-NEXT: s_addc_u32 s0, 1, 0
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18 | 18 | ; CHECK-NEXT: ; return to shader part epilog
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19 |
| - %pair = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val0, i32 %val1) |
20 |
| - %carryout = extractvalue {i32, i1} %pair, 1 |
21 |
| - %add_overflow = sext i1 %carryout to i32 |
22 |
| - %cmp_carryout = icmp ult i32 0, %add_overflow |
23 |
| - %zext_carryout = zext i1 %cmp_carryout to i32 |
| 19 | + %pair = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %val0, i32 1) |
| 20 | + %carryout = extractvalue { i32, i1 } %pair, 1 |
| 21 | + %zext_carryout = zext i1 %carryout to i32 |
24 | 22 | %result = add i32 %zext_carryout, 1
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25 | 23 | ret i32 %result
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26 | 24 | }
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