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labrinealabrinea
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changes from last revision
add feature dit
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9 files changed

+40
-31
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9 files changed

+40
-31
lines changed

‎clang/test/CodeGen/aarch64-cpu-supports-target.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ int check_all_feature() {
55
return 1;
66
else if (__builtin_cpu_supports("rdm+lse+fp+simd+crc+sha1+sha2+sha3"))
77
return 2;
8-
else if (__builtin_cpu_supports("aes+pmull+fp16+dpb+dpb2+jscvt"))
8+
else if (__builtin_cpu_supports("aes+pmull+fp16+dit+dpb+dpb2+jscvt"))
99
return 3;
1010
else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh"))
1111
return 4;

‎clang/test/CodeGen/aarch64-fmv-dependencies.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,9 @@ __attribute__((target_version("crc"))) int fmv(void) { return 0; }
1818
// CHECK: define dso_local i32 @fmv._Mdgh() #[[ATTR0:[0-9]+]] {
1919
__attribute__((target_version("dgh"))) int fmv(void) { return 0; }
2020

21+
// CHECK: define dso_local i32 @fmv._Mdit() #[[dit:[0-9]+]] {
22+
__attribute__((target_version("dit"))) int fmv(void) { return 0; }
23+
2124
// CHECK: define dso_local i32 @fmv._Mdotprod() #[[dotprod:[0-9]+]] {
2225
__attribute__((target_version("dotprod"))) int fmv(void) { return 0; }
2326

@@ -155,6 +158,7 @@ int caller() {
155158
// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
156159
// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
157160
// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
161+
// CHECK: attributes #[[dit]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a"
158162
// CHECK: attributes #[[dotprod]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a"
159163
// CHECK: attributes #[[dpb]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
160164
// CHECK: attributes #[[dpb2]] = { {{.*}} "target-features"="+ccdp,+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"

‎clang/test/CodeGen/attr-target-version.c‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ int foo() {
2727
inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; }
2828
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
2929
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
30-
inline int __attribute__((target_version("bf16"))) fmv_inline(void) { return 8; }
30+
inline int __attribute__((target_version("dit+bf16"))) fmv_inline(void) { return 8; }
3131
inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
3232
inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
3333
inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
@@ -680,7 +680,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
680680
//
681681
//
682682
// CHECK: Function Attrs: noinline nounwind optnone
683-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16
683+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Mdit
684684
// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
685685
// CHECK-NEXT: entry:
686686
// CHECK-NEXT: ret i32 8
@@ -845,68 +845,68 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
845845
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve
846846
// CHECK: resolver_else14:
847847
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
848-
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 20971520
849-
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 20971520
848+
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 134348800
849+
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 134348800
850850
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
851851
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
852852
// CHECK: resolver_return15:
853-
// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc
853+
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Mdit
854854
// CHECK: resolver_else16:
855855
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
856-
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 8650752
857-
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 8650752
856+
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520
857+
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971520
858858
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
859859
// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
860860
// CHECK: resolver_return17:
861-
// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2
861+
// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc
862862
// CHECK: resolver_else18:
863863
// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
864-
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 1572864
865-
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 1572864
864+
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 8650752
865+
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 8650752
866866
// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]]
867867
// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]]
868868
// CHECK: resolver_return19:
869-
// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt
869+
// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2
870870
// CHECK: resolver_else20:
871871
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
872-
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 520
873-
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 520
872+
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 1572864
873+
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1572864
874874
// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]]
875875
// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]]
876876
// CHECK: resolver_return21:
877-
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd
877+
// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt
878878
// CHECK: resolver_else22:
879879
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
880-
// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 32784
881-
// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 32784
880+
// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 520
881+
// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 520
882882
// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]]
883883
// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]]
884884
// CHECK: resolver_return23:
885-
// CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod
885+
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd
886886
// CHECK: resolver_else24:
887887
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
888-
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 192
889-
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 192
888+
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 32784
889+
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 32784
890890
// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]]
891891
// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]
892892
// CHECK: resolver_return25:
893-
// CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm
893+
// CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod
894894
// CHECK: resolver_else26:
895895
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
896-
// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 288
897-
// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 288
896+
// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 192
897+
// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 192
898898
// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]]
899899
// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]]
900900
// CHECK: resolver_return27:
901-
// CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4
901+
// CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm
902902
// CHECK: resolver_else28:
903903
// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
904-
// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 134217728
905-
// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 134217728
904+
// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 288
905+
// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 288
906906
// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]]
907907
// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]]
908908
// CHECK: resolver_return29:
909-
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16
909+
// CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4
910910
// CHECK: resolver_else30:
911911
// CHECK-NEXT: ret ptr @fmv_inline.default
912912
//

‎clang/test/Sema/attr-target-version.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ int __attribute__((target_version("lse"))) main(void) { return 1; }
4444

4545
// It is ok for the default version to appear first.
4646
int default_first(void) { return 1; }
47-
int __attribute__((target_version("lse"))) default_first(void) { return 2; }
47+
int __attribute__((target_version("dit"))) default_first(void) { return 2; }
4848
int __attribute__((target_version("mops"))) default_first(void) { return 3; }
4949

5050
// It is ok if the default version is between other versions.
@@ -77,7 +77,7 @@ void __attribute__((target_version("rdm+rng+crc"))) redef(void) {}
7777
void __attribute__((target_version("rdm+rng+crc"))) redef(void) {}
7878

7979
int def(void);
80-
void __attribute__((target_version("lse"))) nodef(void);
80+
void __attribute__((target_version("dit"))) nodef(void);
8181
void __attribute__((target_version("ls64"))) nodef(void);
8282
void __attribute__((target_version("aes"))) ovl(void);
8383
void __attribute__((target_version("default"))) ovl(void);

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ enum CPUFeatures {
3939
RESERVED_FEAT_AES, // previously used and now ABI legacy
4040
FEAT_PMULL,
4141
FEAT_FP16,
42-
RESERVED_FEAT_DIT, // previously used and now ABI legacy
42+
FEAT_DIT,
4343
FEAT_DPB,
4444
FEAT_DPB2,
4545
FEAT_JSCVT,

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ void __init_cpu_features_resolver(void) {
8585
CHECK_BIT(CAP_BIT_FEAT_DPB2, FEAT_DPB2);
8686
CHECK_BIT(CAP_BIT_FEAT_BF16, FEAT_BF16);
8787
CHECK_BIT(CAP_BIT_FEAT_I8MM, FEAT_I8MM);
88+
CHECK_BIT(CAP_BIT_FEAT_DIT, FEAT_DIT);
8889
CHECK_BIT(CAP_BIT_FEAT_FP16, FEAT_FP16);
8990
CHECK_BIT(CAP_BIT_FEAT_SSBS, FEAT_SSBS2);
9091
CHECK_BIT(CAP_BIT_FEAT_BTI, FEAT_BTI);
@@ -120,6 +121,7 @@ void __init_cpu_features_resolver(void) {
120121
{"hw.optional.arm.FEAT_SHA3", FEAT_SHA3},
121122
{"hw.optional.arm.FEAT_PMULL", FEAT_PMULL},
122123
{"hw.optional.arm.FEAT_FP16", FEAT_FP16},
124+
{"hw.optional.arm.FEAT_DIT", FEAT_DIT},
123125
{"hw.optional.arm.FEAT_DPB", FEAT_DPB},
124126
{"hw.optional.arm.FEAT_DPB2", FEAT_DPB2},
125127
{"hw.optional.arm.FEAT_JSCVT", FEAT_JSCVT},

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,8 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
2929
setCPUFeature(FEAT_FP16FML);
3030
if (hwcap & HWCAP_FPHP)
3131
setCPUFeature(FEAT_FP16);
32+
if (hwcap & HWCAP_DIT)
33+
setCPUFeature(FEAT_DIT);
3234
if (hwcap & HWCAP_ASIMDRDM)
3335
setCPUFeature(FEAT_RDM);
3436
if (hwcap & HWCAP_SHA2)

‎llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ enum CPUFeatures {
3939
RESERVED_FEAT_AES, // previously used and now ABI legacy
4040
FEAT_PMULL,
4141
FEAT_FP16,
42-
RESERVED_FEAT_DIT, // previously used and now ABI legacy
42+
FEAT_DIT,
4343
FEAT_DPB,
4444
FEAT_DPB2,
4545
FEAT_JSCVT,

‎llvm/lib/Target/AArch64/AArch64FMV.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>;
4242
def : FMVExtension<"bti", "FEAT_BTI", "+bti", 510>;
4343
def : FMVExtension<"crc", "FEAT_CRC", "+crc", 110>;
4444
def : FMVExtension<"dgh", "FEAT_DGH", "", 260>;
45+
def : FMVExtension<"dit", "FEAT_DIT", "+dit", 180>;
4546
def : FMVExtension<"dotprod", "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
4647
def : FMVExtension<"dpb", "FEAT_DPB", "+ccpp", 190>;
4748
def : FMVExtension<"dpb2", "FEAT_DPB2", "+ccpp,+ccdp", 200>;

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