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Andres-SalamancaAndres-Salamanca
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[CIR] Fix alignment when lowering set/get bitfield operations
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7 files changed

+95
-72
lines changed

7 files changed

+95
-72
lines changed

‎clang/include/clang/CIR/Dialect/IR/CIROps.td‎

Lines changed: 24 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1720,20 +1720,24 @@ def SetBitfieldOp : CIR_Op<"set_bitfield"> {
17201720
%2 = cir.load %0 : !cir.ptr<!cir.ptr<!record_type>>, !cir.ptr<!record_type>
17211721
%3 = cir.get_member %2[1] {name = "e"} : !cir.ptr<!record_type>
17221722
-> !cir.ptr<!u16i>
1723-
%4 = cir.set_bitfield(#bfi_e, %3 : !cir.ptr<!u16i>, %1 : !s32i) -> !s32i
1723+
%4 = cir.set_bitfield align(4) (#bfi_e, %3 : !cir.ptr<!u16i>, %1 : !s32i)
1724+
-> !s32i
17241725
```
17251726
}];
17261727

17271728
let arguments = (ins
17281729
Arg<CIR_PointerType, "the address to store the value", [MemWrite]>:$addr,
17291730
CIR_AnyType:$src,
17301731
BitfieldInfoAttr:$bitfield_info,
1732+
OptionalAttr<I64Attr>:$alignment,
17311733
UnitAttr:$is_volatile
17321734
);
17331735

17341736
let results = (outs CIR_IntType:$result);
17351737

1736-
let assemblyFormat = [{ `(`$bitfield_info`,` $addr`:`qualified(type($addr))`,`
1738+
let assemblyFormat = [{
1739+
(`align` `(` $alignment^ `)`)?
1740+
`(`$bitfield_info`,` $addr`:`qualified(type($addr))`,`
17371741
$src`:`type($src) `)` attr-dict `->` type($result) }];
17381742

17391743
let builders = [
@@ -1745,14 +1749,18 @@ def SetBitfieldOp : CIR_Op<"set_bitfield"> {
17451749
"unsigned":$size,
17461750
"unsigned":$offset,
17471751
"bool":$is_signed,
1748-
"bool":$is_volatile
1752+
"bool":$is_volatile,
1753+
CArg<"unsigned", "0">:$alignment
17491754
),
17501755
[{
17511756
BitfieldInfoAttr info =
17521757
BitfieldInfoAttr::get($_builder.getContext(),
17531758
name, storage_type,
17541759
size, offset, is_signed);
1755-
build($_builder, $_state, type, addr, src, info, is_volatile);
1760+
build($_builder, $_state, type, addr, src, info,
1761+
alignment == 0 ? IntegerAttr()
1762+
: $_builder.getI64IntegerAttr(alignment),
1763+
is_volatile);
17561764
}]>
17571765
];
17581766
}
@@ -1804,20 +1812,23 @@ def GetBitfieldOp : CIR_Op<"get_bitfield"> {
18041812
%2 = cir.load %0 : !cir.ptr<!cir.ptr<!record_type>>, !cir.ptr<!record_type>
18051813
%3 = cir.get_member %2[1] {name = "e"} : !cir.ptr<!record_type>
18061814
-> !cir.ptr<!u16i>
1807-
%4 = cir.get_bitfield(#bfi_e, %3 : !cir.ptr<!u16i>) -> !s32i
1815+
%4 = cir.get_bitfield align(4) (#bfi_e, %3 : !cir.ptr<!u16i>) -> !s32i
18081816
```
18091817
}];
18101818

18111819
let arguments = (ins
18121820
Arg<CIR_PointerType, "the address to load from", [MemRead]>:$addr,
18131821
BitfieldInfoAttr:$bitfield_info,
1822+
OptionalAttr<I64Attr>:$alignment,
18141823
UnitAttr:$is_volatile
18151824
);
18161825

18171826
let results = (outs CIR_IntType:$result);
18181827

1819-
let assemblyFormat = [{ `(`$bitfield_info `,` $addr attr-dict `:`
1820-
qualified(type($addr)) `)` `->` type($result) }];
1828+
let assemblyFormat = [{
1829+
(`align` `(` $alignment^ `)`)?
1830+
`(`$bitfield_info `,` $addr attr-dict `:`
1831+
qualified(type($addr)) `)` `->` type($result) }];
18211832

18221833
let builders = [
18231834
OpBuilder<(ins "mlir::Type":$type,
@@ -1827,14 +1838,18 @@ def GetBitfieldOp : CIR_Op<"get_bitfield"> {
18271838
"unsigned":$size,
18281839
"unsigned":$offset,
18291840
"bool":$is_signed,
1830-
"bool":$is_volatile
1841+
"bool":$is_volatile,
1842+
CArg<"unsigned", "0">:$alignment
18311843
),
18321844
[{
18331845
BitfieldInfoAttr info =
18341846
BitfieldInfoAttr::get($_builder.getContext(),
18351847
name, storage_type,
18361848
size, offset, is_signed);
1837-
build($_builder, $_state, type, addr, info, is_volatile);
1849+
build($_builder, $_state, type, addr, info,
1850+
alignment == 0 ? IntegerAttr()
1851+
: $_builder.getI64IntegerAttr(alignment),
1852+
is_volatile);
18381853
}]>
18391854
];
18401855
}

‎clang/lib/CIR/CodeGen/CIRGenBuilder.h‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -426,19 +426,21 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy {
426426
mlir::Value createSetBitfield(mlir::Location loc, mlir::Type resultType,
427427
mlir::Value dstAddr, mlir::Type storageType,
428428
mlir::Value src, const CIRGenBitFieldInfo &info,
429-
bool isLvalueVolatile, bool useVolatile) {
430-
return create<cir::SetBitfieldOp>(loc, resultType, dstAddr, storageType,
431-
src, info.name, info.size, info.offset,
432-
info.isSigned, isLvalueVolatile);
429+
bool isLvalueVolatile, bool useVolatile,
430+
unsigned alignment = 0) {
431+
return create<cir::SetBitfieldOp>(
432+
loc, resultType, dstAddr, storageType, src, info.name, info.size,
433+
info.offset, info.isSigned, isLvalueVolatile, alignment);
433434
}
434435

435436
mlir::Value createGetBitfield(mlir::Location loc, mlir::Type resultType,
436437
mlir::Value addr, mlir::Type storageType,
437438
const CIRGenBitFieldInfo &info,
438-
bool isLvalueVolatile, bool useVolatile) {
439-
return create<cir::GetBitfieldOp>(loc, resultType, addr, storageType,
440-
info.name, info.size, info.offset,
441-
info.isSigned, isLvalueVolatile);
439+
bool isLvalueVolatile, bool useVolatile,
440+
unsigned alignment = 0) {
441+
return create<cir::GetBitfieldOp>(
442+
loc, resultType, addr, storageType, info.name, info.size, info.offset,
443+
info.isSigned, isLvalueVolatile, alignment);
442444
}
443445
};
444446

‎clang/lib/CIR/CodeGen/CIRGenExpr.cpp‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -337,9 +337,10 @@ mlir::Value CIRGenFunction::emitStoreThroughBitfieldLValue(RValue src,
337337

338338
mlir::Value dstAddr = dst.getAddress().getPointer();
339339

340-
return builder.createSetBitfield(dstAddr.getLoc(), resLTy, dstAddr,
341-
ptr.getElementType(), src.getValue(), info,
342-
dst.isVolatileQualified(), useVolatile);
340+
return builder.createSetBitfield(
341+
dstAddr.getLoc(), resLTy, dstAddr, ptr.getElementType(), src.getValue(),
342+
info, dst.isVolatileQualified(), useVolatile,
343+
dst.getAddress().getAlignment().getAsAlign().value());
343344
}
344345

345346
RValue CIRGenFunction::emitLoadOfBitfieldLValue(LValue lv, SourceLocation loc) {
@@ -353,7 +354,7 @@ RValue CIRGenFunction::emitLoadOfBitfieldLValue(LValue lv, SourceLocation loc) {
353354

354355
mlir::Value field = builder.createGetBitfield(
355356
getLoc(loc), resLTy, ptr.getPointer(), ptr.getElementType(), info,
356-
lv.isVolatile(), false);
357+
lv.isVolatile(), false, ptr.getAlignment().getAsAlign().value());
357358
assert(!cir::MissingFeatures::opLoadEmitScalarRangeCheck() && "NYI");
358359
return RValue::get(field);
359360
}
@@ -366,7 +367,10 @@ Address CIRGenFunction::getAddrOfBitFieldStorage(LValue base,
366367
cir::PointerType fieldPtr = cir::PointerType::get(fieldType);
367368
cir::GetMemberOp sea = getBuilder().createGetMember(
368369
loc, fieldPtr, base.getPointer(), field->getName(), index);
369-
return Address(sea, CharUnits::One());
370+
auto rec = cast<cir::RecordType>(base.getAddress().getElementType());
371+
CharUnits offset = CharUnits::fromQuantity(
372+
rec.getElementOffset(cgm.getDataLayout().layout, index));
373+
return Address(sea, base.getAlignment().alignmentAtOffset(offset));
370374
}
371375

372376
LValue CIRGenFunction::emitLValueForBitField(LValue base,

‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2555,7 +2555,7 @@ mlir::LogicalResult CIRToLLVMSetBitfieldOpLowering::matchAndRewrite(
25552555
assert(storageSize > size && "Invalid bitfield size.");
25562556

25572557
mlir::Value val = rewriter.create<mlir::LLVM::LoadOp>(
2558-
op.getLoc(), intType, adaptor.getAddr(), /* alignment */ 0,
2558+
op.getLoc(), intType, adaptor.getAddr(), op.getAlignment().value(),
25592559
op.getIsVolatile());
25602560

25612561
srcVal =
@@ -2572,7 +2572,8 @@ mlir::LogicalResult CIRToLLVMSetBitfieldOpLowering::matchAndRewrite(
25722572
}
25732573

25742574
rewriter.create<mlir::LLVM::StoreOp>(op.getLoc(), srcVal, adaptor.getAddr(),
2575-
/* alignment */ 0, op.getIsVolatile());
2575+
op.getAlignment().value(),
2576+
op.getIsVolatile());
25762577

25772578
mlir::Type resultTy = getTypeConverter()->convertType(op.getType());
25782579

@@ -2646,7 +2647,8 @@ mlir::LogicalResult CIRToLLVMGetBitfieldOpLowering::matchAndRewrite(
26462647
computeBitfieldIntType(storageType, context, storageSize);
26472648

26482649
mlir::Value val = rewriter.create<mlir::LLVM::LoadOp>(
2649-
op.getLoc(), intType, adaptor.getAddr(), 0, op.getIsVolatile());
2650+
op.getLoc(), intType, adaptor.getAddr(), op.getAlignment().value(),
2651+
op.getIsVolatile());
26502652
val = rewriter.create<mlir::LLVM::BitcastOp>(op.getLoc(), intType, val);
26512653

26522654
if (info.getIsSigned()) {

‎clang/test/CIR/CodeGen/bitfields.c‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -87,14 +87,14 @@ int load_field(S* s) {
8787
// CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_S>, !cir.ptr<!cir.ptr<!rec_S>>, ["s", init]
8888
// CIR: [[TMP1:%.*]] = cir.load{{.*}} [[TMP0]] : !cir.ptr<!cir.ptr<!rec_S>>, !cir.ptr<!rec_S>
8989
// CIR: [[TMP2:%.*]] = cir.get_member [[TMP1]][0] {name = "c"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>
90-
// CIR: [[TMP3:%.*]] = cir.get_bitfield(#bfi_c, [[TMP2]] : !cir.ptr<!u64i>) -> !s32i
90+
// CIR: [[TMP3:%.*]] = cir.get_bitfield align(4) (#bfi_c, [[TMP2]] : !cir.ptr<!u64i>) -> !s32i
9191

9292
// LLVM: define dso_local i32 @load_field
9393
// LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8
9494
// LLVM: [[TMP1:%.*]] = alloca i32, i64 1, align 4
9595
// LLVM: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8
9696
// LLVM: [[TMP3:%.*]] = getelementptr %struct.S, ptr [[TMP2]], i32 0, i32 0
97-
// LLVM: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 8
97+
// LLVM: [[TMP4:%.*]] = load i64, ptr [[TMP3]], align 4
9898
// LLVM: [[TMP5:%.*]] = shl i64 [[TMP4]], 15
9999
// LLVM: [[TMP6:%.*]] = ashr i64 [[TMP5]], 47
100100
// LLVM: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
@@ -115,13 +115,13 @@ unsigned int load_field_unsigned(A* s) {
115115
//CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_A>, !cir.ptr<!cir.ptr<!rec_A>>, ["s", init] {alignment = 8 : i64}
116116
//CIR: [[TMP1:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_A>>, !cir.ptr<!rec_A>
117117
//CIR: [[TMP2:%.*]] = cir.get_member [[TMP1]][3] {name = "more_bits"} : !cir.ptr<!rec_A> -> !cir.ptr<!u16i>
118-
//CIR: [[TMP3:%.*]] = cir.get_bitfield(#bfi_more_bits, [[TMP2]] : !cir.ptr<!u16i>) -> !u32i
118+
//CIR: [[TMP3:%.*]] = cir.get_bitfield align(1) (#bfi_more_bits, [[TMP2]] : !cir.ptr<!u16i>) -> !u32i
119119

120120
//LLVM: define dso_local i32 @load_field_unsigned
121121
//LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8
122122
//LLVM: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
123123
//LLVM: [[TMP2:%.*]] = getelementptr %struct.A, ptr [[TMP1]], i32 0, i32 3
124-
//LLVM: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 2
124+
//LLVM: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 1
125125
//LLVM: [[TMP4:%.*]] = lshr i16 [[TMP3]], 3
126126
//LLVM: [[TMP5:%.*]] = and i16 [[TMP4]], 15
127127
//LLVM: [[TMP6:%.*]] = zext i16 [[TMP5]] to i32
@@ -143,15 +143,15 @@ void store_field() {
143143
// CIR: [[TMP0:%.*]] = cir.alloca !rec_S, !cir.ptr<!rec_S>
144144
// CIR: [[TMP1:%.*]] = cir.const #cir.int<3> : !s32i
145145
// CIR: [[TMP2:%.*]] = cir.get_member [[TMP0]][1] {name = "e"} : !cir.ptr<!rec_S> -> !cir.ptr<!u16i>
146-
// CIR: cir.set_bitfield(#bfi_e, [[TMP2]] : !cir.ptr<!u16i>, [[TMP1]] : !s32i)
146+
// CIR: cir.set_bitfield align(4) (#bfi_e, [[TMP2]] : !cir.ptr<!u16i>, [[TMP1]] : !s32i)
147147

148148
// LLVM: define dso_local void @store_field()
149149
// LLVM: [[TMP0:%.*]] = alloca %struct.S, i64 1, align 4
150150
// LLVM: [[TMP1:%.*]] = getelementptr %struct.S, ptr [[TMP0]], i32 0, i32 1
151-
// LLVM: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 2
151+
// LLVM: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
152152
// LLVM: [[TMP3:%.*]] = and i16 [[TMP2]], -32768
153153
// LLVM: [[TMP4:%.*]] = or i16 [[TMP3]], 3
154-
// LLVM: store i16 [[TMP4]], ptr [[TMP1]], align 2
154+
// LLVM: store i16 [[TMP4]], ptr [[TMP1]], align 4
155155

156156
// OGCG: define dso_local void @store_field()
157157
// OGCG: [[TMP0:%.*]] = alloca %struct.S, align 4
@@ -169,24 +169,24 @@ void store_bitfield_to_bitfield() {
169169
// CIR: cir.func {{.*@store_bitfield_to_bitfield}}
170170
// CIR: [[TMP0:%.*]] = cir.alloca !rec_S, !cir.ptr<!rec_S>, ["s"] {alignment = 4 : i64}
171171
// CIR: [[TMP1:%.*]] = cir.get_member [[TMP0]][0] {name = "c"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>
172-
// CIR: [[TMP2:%.*]] = cir.get_bitfield(#bfi_c, [[TMP1]] : !cir.ptr<!u64i>) -> !s32i
172+
// CIR: [[TMP2:%.*]] = cir.get_bitfield align(4) (#bfi_c, [[TMP1]] : !cir.ptr<!u64i>) -> !s32i
173173
// CIR: [[TMP3:%.*]] = cir.get_member [[TMP0]][0] {name = "a"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>
174-
// CIR: [[TMP4:%.*]] = cir.set_bitfield(#bfi_a, [[TMP3]] : !cir.ptr<!u64i>, [[TMP2]] : !s32i) -> !s32i
174+
// CIR: [[TMP4:%.*]] = cir.set_bitfield align(4) (#bfi_a, [[TMP3]] : !cir.ptr<!u64i>, [[TMP2]] : !s32i) -> !s32i
175175

176176
// LLVM: define dso_local void @store_bitfield_to_bitfield()
177177
// LLVM: [[TMP0:%.*]] = alloca %struct.S, i64 1, align 4
178178
// LLVM: [[TMP1:%.*]] = getelementptr %struct.S, ptr [[TMP0]], i32 0, i32 0
179-
// LLVM: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
179+
// LLVM: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 4
180180
// LLVM: [[TMP3:%.*]] = shl i64 [[TMP2]], 15
181181
// LLVM: [[TMP4:%.*]] = ashr i64 [[TMP3]], 47
182182
// LLVM: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i32
183183
// LLVM: [[TMP6:%.*]] = getelementptr %struct.S, ptr [[TMP0]], i32 0, i32 0
184184
// LLVM: [[TMP7:%.*]] = zext i32 [[TMP5]] to i64
185-
// LLVM: [[TMP8:%.*]] = load i64, ptr [[TMP6]], align 8
185+
// LLVM: [[TMP8:%.*]] = load i64, ptr [[TMP6]], align 4
186186
// LLVM: [[TMP9:%.*]] = and i64 [[TMP7]], 15
187187
// LLVM: [[TMP10:%.*]] = and i64 [[TMP8]], -16
188188
// LLVM: [[TMP11:%.*]] = or i64 [[TMP10]], [[TMP9]]
189-
// LLVM: store i64 [[TMP11]], ptr [[TMP6]], align 8
189+
// LLVM: store i64 [[TMP11]], ptr [[TMP6]], align 4
190190
// LLVM: [[TMP12:%.*]] = shl i64 [[TMP9]], 60
191191
// LLVM: [[TMP13:%.*]] = ashr i64 [[TMP12]], 60
192192
// LLVM: [[TMP15:%.*]] = trunc i64 [[TMP13]] to i32
@@ -222,16 +222,16 @@ void get_volatile(V* v) {
222222
// CIR: [[TMP1:%.*]] = cir.const #cir.int<3> : !s32i
223223
// CIR: [[TMP2:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_V>>, !cir.ptr<!rec_V>
224224
// CIR: [[TMP3:%.*]] = cir.get_member [[TMP2]][0] {name = "b"} : !cir.ptr<!rec_V> -> !cir.ptr<!u64i>
225-
// CIR: [[TMP4:%.*]] = cir.set_bitfield(#bfi_b, [[TMP3]] : !cir.ptr<!u64i>, [[TMP1]] : !s32i) {is_volatile} -> !s32i
225+
// CIR: [[TMP4:%.*]] = cir.set_bitfield align(4) (#bfi_b, [[TMP3]] : !cir.ptr<!u64i>, [[TMP1]] : !s32i) {is_volatile} -> !s32i
226226

227227
// LLVM: define dso_local void @get_volatile
228228
// LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8
229229
// LLVM: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
230230
// LLVM: [[TMP2:%.*]] = getelementptr %struct.V, ptr [[TMP1]], i32 0, i32 0
231-
// LLVM: [[TMP3:%.*]] = load volatile i64, ptr [[TMP2]], align 8
231+
// LLVM: [[TMP3:%.*]] = load volatile i64, ptr [[TMP2]], align 4
232232
// LLVM: [[TMP4:%.*]] = and i64 [[TMP3]], -1095216660481
233233
// LLVM: [[TMP5:%.*]] = or i64 [[TMP4]], 12884901888
234-
// LLVM: store volatile i64 [[TMP5]], ptr [[TMP2]], align 8
234+
// LLVM: store volatile i64 [[TMP5]], ptr [[TMP2]], align 4
235235

236236
// OCGC: define dso_local void @get_volatile
237237
// OCGC: [[TMP0:%.*]] = alloca ptr, align 8
@@ -249,16 +249,16 @@ void set_volatile(V* v) {
249249
//CIR: [[TMP1:%.*]] = cir.const #cir.int<3> : !s32i
250250
//CIR: [[TMP2:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_V>>, !cir.ptr<!rec_V>
251251
//CIR: [[TMP3:%.*]] = cir.get_member [[TMP2]][0] {name = "b"} : !cir.ptr<!rec_V> -> !cir.ptr<!u64i>
252-
//CIR: [[TMP4:%.*]] = cir.set_bitfield(#bfi_b, [[TMP3]] : !cir.ptr<!u64i>, [[TMP1]] : !s32i) {is_volatile} -> !s32i
252+
//CIR: [[TMP4:%.*]] = cir.set_bitfield align(4) (#bfi_b, [[TMP3]] : !cir.ptr<!u64i>, [[TMP1]] : !s32i) {is_volatile} -> !s32i
253253

254254
// LLVM: define dso_local void @set_volatile
255255
// LLVM: [[TMP0:%.*]] = alloca ptr, i64 1, align 8
256256
// LLVM: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
257257
// LLVM: [[TMP2:%.*]] = getelementptr %struct.V, ptr [[TMP1]], i32 0, i32 0
258-
// LLVM: [[TMP3:%.*]] = load volatile i64, ptr [[TMP2]], align 8
258+
// LLVM: [[TMP3:%.*]] = load volatile i64, ptr [[TMP2]], align 4
259259
// LLVM: [[TMP4:%.*]] = and i64 [[TMP3]], -1095216660481
260260
// LLVM: [[TMP5:%.*]] = or i64 [[TMP4]], 12884901888
261-
// LLVM: store volatile i64 [[TMP5]], ptr [[TMP2]], align 8
261+
// LLVM: store volatile i64 [[TMP5]], ptr [[TMP2]], align 4
262262

263263
// OGCG: define dso_local void @set_volatile
264264
// OGCG: [[TMP0:%.*]] = alloca ptr, align 8
@@ -276,24 +276,24 @@ void unOp(S* s) {
276276
// CIR: [[TMP0:%.*]] = cir.alloca !cir.ptr<!rec_S>, !cir.ptr<!cir.ptr<!rec_S>>, ["s", init] {alignment = 8 : i64}
277277
// CIR: [[TMP1:%.*]] = cir.load align(8) [[TMP0]] : !cir.ptr<!cir.ptr<!rec_S>>, !cir.ptr<!rec_S>
278278
// CIR: [[TMP2:%.*]] = cir.get_member [[TMP1]][0] {name = "d"} : !cir.ptr<!rec_S> -> !cir.ptr<!u64i>
279-
// CIR: [[TMP3:%.*]] = cir.get_bitfield(#bfi_d, [[TMP2]] : !cir.ptr<!u64i>) -> !s32i
279+
// CIR: [[TMP3:%.*]] = cir.get_bitfield align(4) (#bfi_d, [[TMP2]] : !cir.ptr<!u64i>) -> !s32i
280280
// CIR: [[TMP4:%.*]] = cir.unary(inc, [[TMP3]]) nsw : !s32i, !s32i
281-
// CIR: cir.set_bitfield(#bfi_d, [[TMP2]] : !cir.ptr<!u64i>, [[TMP4]] : !s32i)
281+
// CIR: cir.set_bitfield align(4) (#bfi_d, [[TMP2]] : !cir.ptr<!u64i>, [[TMP4]] : !s32i)
282282

283283
// LLVM: define {{.*@unOp}}
284284
// LLVM: [[TMP0:%.*]] = getelementptr %struct.S, ptr [[LOAD0:%.*]], i32 0, i32 0
285-
// LLVM: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8
285+
// LLVM: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 4
286286
// LLVM: [[TMP2:%.*]] = shl i64 [[TMP1]], 13
287287
// LLVM: [[TMP3:%.*]] = ashr i64 [[TMP2]], 62
288288
// LLVM: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
289289
// LLVM: [[TMP5:%.*]] = add nsw i32 [[TMP4]], 1
290290
// LLVM: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
291-
// LLVM: [[TMP7:%.*]] = load i64, ptr [[TMP0]], align 8
291+
// LLVM: [[TMP7:%.*]] = load i64, ptr [[TMP0]], align 4
292292
// LLVM: [[TMP8:%.*]] = and i64 [[TMP6]], 3
293293
// LLVM: [[TMP9:%.*]] = shl i64 [[TMP8]], 49
294294
// LLVM: [[TMP10:%.*]] = and i64 [[TMP7]], -1688849860263937
295295
// LLVM: [[TMP11:%.*]] = or i64 [[TMP10]], [[TMP9]]
296-
// LLVM: store i64 [[TMP11]], ptr [[TMP0]], align 8
296+
// LLVM: store i64 [[TMP11]], ptr [[TMP0]], align 4
297297
// LLVM: [[TMP12:%.*]] = shl i64 [[TMP8]], 62
298298
// LLVM: [[TMP13:%.*]] = ashr i64 [[TMP12]], 62
299299
// LLVM: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32

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