@@ -2545,11 +2545,10 @@ void mlir::populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter,
25452545 AMDGPUDPPLowering, MemoryCounterWaitOpLowering, LDSBarrierOpLowering,
25462546 SchedBarrierOpLowering, MFMAOpLowering, ScaledMFMAOpLowering,
25472547 WMMAOpLowering, ScaledWMMAOpLowering, ExtPackedFp8OpLowering,
2548- ScaledExtPacked816OpLowering,
2549- ScaledExtPackedOpLowering, PackedScaledTruncOpLowering,
2550- PackedTrunc2xFp8OpLowering, PackedStochRoundFp8OpLowering,
2551- GatherToLDSOpLowering, TransposeLoadOpLowering,
2552- AMDGPUPermlaneLowering, AMDGPUMakeDmaBaseLowering>(converter,
2553- chipset);
2548+ ScaledExtPacked816OpLowering, ScaledExtPackedOpLowering,
2549+ PackedScaledTruncOpLowering, PackedTrunc2xFp8OpLowering,
2550+ PackedStochRoundFp8OpLowering, GatherToLDSOpLowering,
2551+ TransposeLoadOpLowering, AMDGPUPermlaneLowering,
2552+ AMDGPUMakeDmaBaseLowering>(converter, chipset);
25542553 patterns.add <AMDGPUSwizzleBitModeLowering>(converter);
25552554}
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