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[VPlan] Support multiple F(Max|Min)Num reductions.
Generalize handleMaxMinNumReductions to handle any number of F(Max|Min)Num reductions by collecting a vector of reductions to convert. We then add NaN checks for all of them, followed by adjusting the branch controlling the vector loop region, and updating the resume phis.
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6 files changed

+262
-86
lines changed

6 files changed

+262
-86
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp‎

Lines changed: 49 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -826,7 +826,7 @@ bool VPlanTransforms::handleMaxMinNumReductions(VPlan &Plan) {
826826
};
827827

828828
VPRegionBlock *LoopRegion = Plan.getVectorLoopRegion();
829-
VPReductionPHIRecipe *RedPhiR = nullptr;
829+
SmallVector<VPReductionPHIRecipe *> ReductionsToConvert;
830830
bool HasUnsupportedPhi = false;
831831
for (auto &R : LoopRegion->getEntryBasicBlock()->phis()) {
832832
if (isa<VPCanonicalIVPHIRecipe, VPWidenIntOrFpInductionRecipe>(&R))
@@ -837,19 +837,15 @@ bool VPlanTransforms::handleMaxMinNumReductions(VPlan &Plan) {
837837
HasUnsupportedPhi = true;
838838
continue;
839839
}
840-
// For now, only a single reduction is supported.
841-
// TODO: Support multiple MaxNum/MinNum reductions and other reductions.
842-
if (RedPhiR)
843-
return false;
844840
if (Cur->getRecurrenceKind() != RecurKind::FMaxNum &&
845841
Cur->getRecurrenceKind() != RecurKind::FMinNum) {
846842
HasUnsupportedPhi = true;
847843
continue;
848844
}
849-
RedPhiR = Cur;
845+
ReductionsToConvert.push_back(Cur);
850846
}
851847

852-
if (!RedPhiR)
848+
if (ReductionsToConvert.empty())
853849
return true;
854850

855851
// We won't be able to resume execution in the scalar tail, if there are
@@ -858,15 +854,6 @@ bool VPlanTransforms::handleMaxMinNumReductions(VPlan &Plan) {
858854
if (HasUnsupportedPhi || !Plan.hasScalarTail())
859855
return false;
860856

861-
VPValue *MinMaxOp = GetMinMaxCompareValue(RedPhiR);
862-
if (!MinMaxOp)
863-
return false;
864-
865-
RecurKind RedPhiRK = RedPhiR->getRecurrenceKind();
866-
assert((RedPhiRK == RecurKind::FMaxNum || RedPhiRK == RecurKind::FMinNum) &&
867-
"unsupported reduction");
868-
(void)RedPhiRK;
869-
870857
/// Check if the vector loop of \p Plan can early exit and restart
871858
/// execution of last vector iteration in the scalar loop. This requires all
872859
/// recipes up to early exit point be side-effect free as they are
@@ -884,52 +871,69 @@ bool VPlanTransforms::handleMaxMinNumReductions(VPlan &Plan) {
884871
}
885872

886873
VPBasicBlock *LatchVPBB = LoopRegion->getExitingBasicBlock();
874+
VPBasicBlock *MiddleVPBB = Plan.getMiddleBlock();
875+
VPBuilder MiddleBuilder(MiddleVPBB, MiddleVPBB->begin());
887876
VPBuilder Builder(LatchVPBB->getTerminator());
888-
auto *LatchExitingBranch = cast<VPInstruction>(LatchVPBB->getTerminator());
889-
assert(LatchExitingBranch->getOpcode() == VPInstruction::BranchOnCount &&
877+
VPValue *AnyNaN = nullptr;
878+
SmallPtrSet<VPValue *, 2> RdxResults;
879+
for (VPReductionPHIRecipe *RedPhiR : ReductionsToConvert) {
880+
VPValue *MinMaxOp = GetMinMaxCompareValue(RedPhiR);
881+
if (!MinMaxOp)
882+
return false;
883+
884+
RecurKind RedPhiRK = RedPhiR->getRecurrenceKind();
885+
assert((RedPhiRK == RecurKind::FMaxNum || RedPhiRK == RecurKind::FMinNum) &&
886+
"unsupported reduction");
887+
(void)RedPhiRK;
888+
889+
VPValue *IsNaN = Builder.createFCmp(CmpInst::FCMP_UNO, MinMaxOp, MinMaxOp);
890+
VPValue *HasNaN = Builder.createNaryOp(VPInstruction::AnyOf, {IsNaN});
891+
if (AnyNaN)
892+
AnyNaN = Builder.createOr(AnyNaN, HasNaN);
893+
else
894+
AnyNaN = HasNaN;
895+
896+
// If we exit early due to NaNs, compute the final reduction result based
897+
// on the reduction phi at the beginning of the last vector iteration.
898+
auto *RdxResult = find_singleton<VPSingleDefRecipe>(
899+
RedPhiR->users(), [](VPUser *U, bool) -> VPSingleDefRecipe * {
900+
auto *VPI = dyn_cast<VPInstruction>(U);
901+
if (VPI && VPI->getOpcode() == VPInstruction::ComputeReductionResult)
902+
return VPI;
903+
return nullptr;
904+
});
905+
906+
auto *NewSel =
907+
MiddleBuilder.createSelect(HasNaN, RedPhiR, RdxResult->getOperand(1));
908+
RdxResult->setOperand(1, NewSel);
909+
RdxResults.insert(RdxResult);
910+
}
911+
912+
auto *LatchExitingBranch = LatchVPBB->getTerminator();
913+
assert(match(LatchExitingBranch, m_BranchOnCount(m_VPValue(), m_VPValue())) &&
890914
"Unexpected terminator");
891915
auto *IsLatchExitTaken =
892916
Builder.createICmp(CmpInst::ICMP_EQ, LatchExitingBranch->getOperand(0),
893917
LatchExitingBranch->getOperand(1));
894-
895-
VPValue *IsNaN = Builder.createFCmp(CmpInst::FCMP_UNO, MinMaxOp, MinMaxOp);
896-
VPValue *AnyNaN = Builder.createNaryOp(VPInstruction::AnyOf, {IsNaN});
897918
auto *AnyExitTaken =
898919
Builder.createNaryOp(Instruction::Or, {AnyNaN, IsLatchExitTaken});
899920
Builder.createNaryOp(VPInstruction::BranchOnCond, AnyExitTaken);
900921
LatchExitingBranch->eraseFromParent();
901922

902-
// If we exit early due to NaNs, compute the final reduction result based on
903-
// the reduction phi at the beginning of the last vector iteration.
904-
auto *RdxResult = find_singleton<VPSingleDefRecipe>(
905-
RedPhiR->users(), [](VPUser *U, bool) -> VPSingleDefRecipe * {
906-
auto *VPI = dyn_cast<VPInstruction>(U);
907-
if (VPI && VPI->getOpcode() == VPInstruction::ComputeReductionResult)
908-
return VPI;
909-
return nullptr;
910-
});
911-
912-
auto *MiddleVPBB = Plan.getMiddleBlock();
913-
Builder.setInsertPoint(MiddleVPBB, MiddleVPBB->begin());
914-
auto *NewSel =
915-
Builder.createSelect(AnyNaN, RedPhiR, RdxResult->getOperand(1));
916-
RdxResult->setOperand(1, NewSel);
917-
918-
auto *ScalarPH = Plan.getScalarPreheader();
919923
// Update resume phis for inductions in the scalar preheader. If AnyNaN is
920924
// true, the resume from the start of the last vector iteration via the
921925
// canonical IV, otherwise from the original value.
922-
for (auto &R : ScalarPH->phis()) {
926+
for (auto &R : Plan.getScalarPreheader()->phis()) {
923927
auto *ResumeR = cast<VPPhi>(&R);
924928
VPValue *VecV = ResumeR->getOperand(0);
925-
if (VecV == RdxResult)
929+
if (RdxResults.contains(VecV))
926930
continue;
927931
if (auto *DerivedIV = dyn_cast<VPDerivedIVRecipe>(VecV)) {
928932
if (DerivedIV->getNumUsers() == 1 &&
929933
DerivedIV->getOperand(1) == &Plan.getVectorTripCount()) {
930-
auto *NewSel = Builder.createSelect(AnyNaN, Plan.getCanonicalIV(),
931-
&Plan.getVectorTripCount());
932-
DerivedIV->moveAfter(&*Builder.getInsertPoint());
934+
auto *NewSel = MiddleBuilder.createSelect(AnyNaN, Plan.getCanonicalIV(),
935+
&Plan.getVectorTripCount());
936+
DerivedIV->moveAfter(&*MiddleBuilder.getInsertPoint());
933937
DerivedIV->setOperand(1, NewSel);
934938
continue;
935939
}
@@ -941,7 +945,8 @@ bool VPlanTransforms::handleMaxMinNumReductions(VPlan &Plan) {
941945
"FMaxNum/FMinNum reduction.\n");
942946
return false;
943947
}
944-
auto *NewSel = Builder.createSelect(AnyNaN, Plan.getCanonicalIV(), VecV);
948+
auto *NewSel =
949+
MiddleBuilder.createSelect(AnyNaN, Plan.getCanonicalIV(), VecV);
945950
ResumeR->setOperand(0, NewSel);
946951
}
947952

‎llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll‎

Lines changed: 75 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ define float @fmaxnum(ptr %src, i64 %n) {
5959
; CHECK-NEXT: [[TMP7]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]])
6060
; CHECK-NEXT: [[TMP8]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI1]], <4 x float> [[WIDE_LOAD2]])
6161
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8
62-
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
6362
; CHECK-NEXT: [[TMP3:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]
6463
; CHECK-NEXT: [[TMP4:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD2]], [[WIDE_LOAD2]]
6564
; CHECK-NEXT: [[TMP18:%.*]] = freeze <4 x i1> [[TMP3]]
@@ -68,6 +67,7 @@ define float @fmaxnum(ptr %src, i64 %n) {
6867
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
6968
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[TMP6]], i64 0
7069
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
70+
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
7171
; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP6]], [[TMP9]]
7272
; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
7373
; CHECK: [[MIDDLE_BLOCK]]:
@@ -118,23 +118,86 @@ define float @test_fmax_and_fmin(ptr %src.0, ptr %src.1, i64 %n) {
118118
; CHECK-LABEL: define float @test_fmax_and_fmin(
119119
; CHECK-SAME: ptr [[SRC_0:%.*]], ptr [[SRC_1:%.*]], i64 [[N:%.*]]) {
120120
; CHECK-NEXT: [[ENTRY:.*]]:
121-
; CHECK-NEXT: br label %[[LOOP:.*]]
122-
; CHECK: [[LOOP]]:
123-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
124-
; CHECK-NEXT: [[MIN:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]
125-
; CHECK-NEXT: [[MAX:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
121+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
122+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
123+
; CHECK: [[VECTOR_PH]]:
124+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
125+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
126+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
127+
; CHECK: [[VECTOR_BODY]]:
128+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
129+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
130+
; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
131+
; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
132+
; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x float> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
126133
; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_0]], i64 [[IV]]
127134
; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_1]], i64 [[IV]]
128-
; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[GEP_SRC_0]], align 4
129-
; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 4
135+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[GEP_SRC_0]], i32 4
136+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[GEP_SRC_0]], align 4
137+
; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
138+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw float, ptr [[GEP_SRC_1]], i32 4
139+
; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[GEP_SRC_1]], align 4
140+
; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP3]], align 4
141+
; CHECK-NEXT: [[TMP4]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI2]], <4 x float> [[WIDE_LOAD]])
142+
; CHECK-NEXT: [[TMP5]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI3]], <4 x float> [[WIDE_LOAD4]])
143+
; CHECK-NEXT: [[TMP6]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD5]])
144+
; CHECK-NEXT: [[TMP7]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[VEC_PHI1]], <4 x float> [[WIDE_LOAD6]])
145+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8
146+
; CHECK-NEXT: [[TMP8:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD5]], [[WIDE_LOAD5]]
147+
; CHECK-NEXT: [[TMP9:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD6]], [[WIDE_LOAD6]]
148+
; CHECK-NEXT: [[TMP10:%.*]] = freeze <4 x i1> [[TMP8]]
149+
; CHECK-NEXT: [[TMP11:%.*]] = freeze <4 x i1> [[TMP9]]
150+
; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i1> [[TMP10]], [[TMP11]]
151+
; CHECK-NEXT: [[TMP13:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP12]])
152+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[TMP13]], i64 0
153+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
154+
; CHECK-NEXT: [[TMP14:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]
155+
; CHECK-NEXT: [[TMP15:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD4]], [[WIDE_LOAD4]]
156+
; CHECK-NEXT: [[TMP16:%.*]] = freeze <4 x i1> [[TMP14]]
157+
; CHECK-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP15]]
158+
; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP17]]
159+
; CHECK-NEXT: [[TMP19:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP18]])
160+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <4 x i1> poison, i1 [[TMP19]], i64 0
161+
; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT7]], <4 x i1> poison, <4 x i32> zeroinitializer
162+
; CHECK-NEXT: [[TMP20:%.*]] = or i1 [[TMP13]], [[TMP19]]
163+
; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
164+
; CHECK-NEXT: [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
165+
; CHECK-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
166+
; CHECK: [[MIDDLE_BLOCK]]:
167+
; CHECK-NEXT: [[TMP23:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP6]]
168+
; CHECK-NEXT: [[TMP24:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP7]]
169+
; CHECK-NEXT: [[TMP25:%.*]] = select <4 x i1> [[BROADCAST_SPLAT8]], <4 x float> [[VEC_PHI2]], <4 x float> [[TMP4]]
170+
; CHECK-NEXT: [[TMP26:%.*]] = select <4 x i1> [[BROADCAST_SPLAT8]], <4 x float> [[VEC_PHI3]], <4 x float> [[TMP5]]
171+
; CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP20]], i64 [[IV]], i64 [[N_VEC]]
172+
; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP23]], <4 x float> [[TMP24]])
173+
; CHECK-NEXT: [[TMP28:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[RDX_MINMAX]])
174+
; CHECK-NEXT: [[RDX_MINMAX9:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP25]], <4 x float> [[TMP26]])
175+
; CHECK-NEXT: [[TMP29:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[RDX_MINMAX9]])
176+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
177+
; CHECK-NEXT: [[TMP30:%.*]] = xor i1 [[TMP20]], true
178+
; CHECK-NEXT: [[TMP31:%.*]] = and i1 [[CMP_N]], [[TMP30]]
179+
; CHECK-NEXT: br i1 [[TMP31]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
180+
; CHECK: [[SCALAR_PH]]:
181+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP27]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
182+
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP28]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
183+
; CHECK-NEXT: [[BC_MERGE_RDX10:%.*]] = phi float [ [[TMP29]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
184+
; CHECK-NEXT: br label %[[LOOP:.*]]
185+
; CHECK: [[LOOP]]:
186+
; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
187+
; CHECK-NEXT: [[MIN:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]
188+
; CHECK-NEXT: [[MAX:%.*]] = phi float [ [[BC_MERGE_RDX10]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
189+
; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_0]], i64 [[IV1]]
190+
; CHECK-NEXT: [[GEP_SRC_3:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_1]], i64 [[IV1]]
191+
; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[GEP_SRC_2]], align 4
192+
; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_3]], align 4
130193
; CHECK-NEXT: [[MAX_NEXT]] = tail call noundef float @llvm.maxnum.f32(float [[MAX]], float [[L_0]])
131194
; CHECK-NEXT: [[MIN_NEXT]] = tail call noundef float @llvm.minnum.f32(float [[MIN]], float [[L_1]])
132-
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
195+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1
133196
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
134-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
197+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
135198
; CHECK: [[EXIT]]:
136-
; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]
137-
; CHECK-NEXT: [[MIN_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]
199+
; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ], [ [[TMP29]], %[[MIDDLE_BLOCK]] ]
200+
; CHECK-NEXT: [[MIN_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ], [ [[TMP28]], %[[MIDDLE_BLOCK]] ]
138201
; CHECK-NEXT: [[SUB:%.*]] = fsub float [[MAX_NEXT_LCSSA]], [[MIN_NEXT_LCSSA]]
139202
; CHECK-NEXT: ret float [[SUB]]
140203
;

‎llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ define float @fminnum(ptr %src, i64 %n) {
5959
; CHECK-NEXT: [[TMP7]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]])
6060
; CHECK-NEXT: [[TMP8]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[VEC_PHI1]], <4 x float> [[WIDE_LOAD2]])
6161
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 8
62-
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
6362
; CHECK-NEXT: [[TMP3:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]
6463
; CHECK-NEXT: [[TMP4:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD2]], [[WIDE_LOAD2]]
6564
; CHECK-NEXT: [[TMP15:%.*]] = freeze <4 x i1> [[TMP3]]
@@ -68,6 +67,7 @@ define float @fminnum(ptr %src, i64 %n) {
6867
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
6968
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[TMP6]], i64 0
7069
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer
70+
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
7171
; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP6]], [[TMP9]]
7272
; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
7373
; CHECK: [[MIDDLE_BLOCK]]:

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