[RISCV] Add BREV8 and ORC_B to hasAllNBitUsers in RISCVOptWInstrs.

Author: topperc

llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

@@ -323,6 +323,11 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
         Worklist.push_back(std::make_pair(UserMI, Bits));
         break;
 
+      case RISCV::BREV8:
+      case RISCV::ORC_B:
+        Worklist.push_back(std::make_pair(UserMI, Bits));
+        break;
+
       case RISCV::PseudoCCMOVGPR:
       case RISCV::PseudoCCMOVGPRNoX0:
         // Either operand 4 or operand 5 is returned by this instruction. If

llvm/test/CodeGen/RISCV/sextw-removal.ll

@@ -1547,10 +1547,9 @@ define signext i32 @test21(i64 %arg1, i64 %arg2, i64 %arg3)  {
 ; RV64ZBB-NEXT:    brev8 a0, a0
 ; RV64ZBB-NEXT:    andi a0, a0, 1234
 ; RV64ZBB-NEXT:    addi a2, a2, 1
-; RV64ZBB-NEXT:    add a0, a0, a1
+; RV64ZBB-NEXT:    addw a0, a0, a1
 ; RV64ZBB-NEXT:    bltu a2, a3, .LBB25_1
 ; RV64ZBB-NEXT:  # %bb.2: # %bb7
-; RV64ZBB-NEXT:    sext.w a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; NOREMOVAL-LABEL: test21:
@@ -1641,10 +1640,9 @@ define signext i32 @test22(i64 %arg1, i64 %arg2, i64 %arg3)  {
 ; RV64ZBB-NEXT:    srli a0, a0, 28
 ; RV64ZBB-NEXT:    andi a0, a0, 1234
 ; RV64ZBB-NEXT:    addi a2, a2, 1
-; RV64ZBB-NEXT:    add a0, a0, a1
+; RV64ZBB-NEXT:    addw a0, a0, a1
 ; RV64ZBB-NEXT:    bltu a2, a3, .LBB26_1
 ; RV64ZBB-NEXT:  # %bb.2: # %bb7
-; RV64ZBB-NEXT:    sext.w a0, a0
 ; RV64ZBB-NEXT:    ret
 ;
 ; NOREMOVAL-LABEL: test22: