fixup! Address comments and failures

Change-Id: I9d9e9aa1c18b995c10b835accb49ef6466fc72eb

Author: hchandel

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

@@ -753,12 +753,12 @@ def QC_C_MILEAVERET   : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
 let Predicates = [HasVendorXqciio, IsRV32] in {
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
   def QC_OUTW : RVInstI<0b100, OPC_CUSTOM_0, (outs),
-                        (ins GPR:$rs3, GPR:$rs1, uimm14lsb00:$imm14),
-                        "qc.outw", "$rs3, ${imm14}(${rs1})"> {
-    bits<5> rs3;
+                        (ins GPR:$rs2, GPR:$rs1, uimm14lsb00:$imm14),
+                        "qc.outw", "$rs2, ${imm14}(${rs1})"> {
+    bits<5> rs2;
     bits<14> imm14;
 
-    let rd = rs3;
+    let rd = rs2;
     let imm12 = imm14{13-2};
   }
 
@@ -889,6 +889,15 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
 // Aliases
 //===----------------------------------------------------------------------===//
 
+let Predicates = [HasVendorXqciio, IsRV32] in {
+let EmitPriority = 0 in {
+  def : InstAlias<"qc.outw $rs2, (${rs1})",
+                  (QC_OUTW GPR:$rs2, GPR:$rs1, 0)>;
+  def : InstAlias<"qc.inw $rd, (${rs1})",
+                  (QC_INW GPRNoX0:$rd, GPR:$rs1, 0)>;
+} // EmitPriority = 0
+} // Predicates = [HasVendorXqciio, IsRV32]
+
 let Predicates = [HasVendorXqcilsm, IsRV32] in {
 let EmitPriority = 0 in {
   def : InstAlias<"qc.swm $rs3, $rs2, (${rs1})",

llvm/test/CodeGen/RISCV/features-info.ll

@@ -32,6 +32,7 @@
 ; CHECK-NEXT:   experimental-xqcics              - 'Xqcics' (Qualcomm uC Conditional Select Extension).
 ; CHECK-NEXT:   experimental-xqcicsr             - 'Xqcicsr' (Qualcomm uC CSR Extension).
 ; CHECK-NEXT:   experimental-xqciint             - 'Xqciint' (Qualcomm uC Interrupts Extension).
+; CHECK-NEXT:   experimental-xqciio              - 'Xqciio' (Qualcomm uC External Input Output Extension).
 ; CHECK-NEXT:   experimental-xqcilb              - 'Xqcilb' (Qualcomm uC Long Branch Extension).
 ; CHECK-NEXT:   experimental-xqcili              - 'Xqcili' (Qualcomm uC Load Large Immediate Extension).
 ; CHECK-NEXT:   experimental-xqcilia             - 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension).

llvm/test/MC/RISCV/xqciio-aliases-valid.s

@@ -0,0 +1,20 @@
+# Xqciio - Qualcomm uC External Input Output extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqciio -M no-aliases --no-print-imm-hex -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqciio --no-print-imm-hex -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: qc.outw t0, 0(a0)
+# CHECK-ENC: encoding: [0x8b,0x42,0x05,0x00]
+qc.outw x5, (x10)
+
+
+# CHECK-INST: qc.inw  t0, 0(a0)
+# CHECK-ENC: encoding: [0x8b,0x52,0x05,0x00]
+qc.inw x5, (x10)