Skip to content

Commit 2ce4915

Browse files
author
anoopkg6
committed
Incorporated code review changes for combineLogicalOpCCMask, which may be used for future work.
1 parent 78cdca5 commit 2ce4915

File tree

1 file changed

+23
-8
lines changed

1 file changed

+23
-8
lines changed

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 23 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9233,39 +9233,54 @@ SystemZTargetLowering::combineLogicalOpCCMask(SDNode *N,
92339233
int Op0CCMaskVal = Op0CCMask->getZExtValue();
92349234
int Op1CCMaskVal = Op1CCMask->getZExtValue();
92359235
if (Opcode == ISD::AND) {
9236-
if ((Op0CCMaskVal ^ Op0CCValidVal) & (Op1CCMaskVal ^ Op1CCValidVal))
9236+
// CC neither in Op0CCMaskVal nor in Op1CCMaskVal.
9237+
if ((Op0CCValidVal ^ (Op0CCMaskVal | Op1CCMaskVal)))
92379238
return SDValue();
92389239
CCMask = Op0CCMaskVal & Op1CCMaskVal;
92399240
CCValid = Op0CCValidVal;
92409241
CCReg = Op0CCReg;
92419242
TrueVal = N0->getOperand(0);
9242-
FalseVal = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i32,
9243+
TrueVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32,
9244+
DAG.getTargetConstant(Op0TrueVal->getZExtValue(),
9245+
SDLoc(N0), MVT::i32),
9246+
DAG.getTargetConstant(Op1TrueVal->getZExtValue(),
9247+
SDLoc(N0), MVT::i32));
9248+
FalseVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32,
92439249
DAG.getTargetConstant(Op0TrueVal->getZExtValue(),
92449250
SDLoc(N0), MVT::i32),
92459251
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
92469252
SDLoc(N0), MVT::i32));
92479253
} else if (Opcode == ISD::OR) {
9254+
// CC in both Op0CCMaskVal and Op1CCMaskVal.
92489255
if (Op0CCMaskVal & Op1CCMaskVal)
92499256
return SDValue();
92509257
CCMask = Op0CCMaskVal | Op1CCMaskVal;
92519258
CCValid = Op0CCValidVal;
92529259
CCReg = Op0CCReg;
9253-
TrueVal = DAG.getNode(ISD::OR, SDLoc(N0), MVT::i32,
9260+
TrueVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32,
92549261
DAG.getTargetConstant(Op0TrueVal->getZExtValue(),
92559262
SDLoc(N0), MVT::i32),
92569263
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
92579264
SDLoc(N0), MVT::i32));
9258-
FalseVal = N0->getOperand(1);
9265+
FalseVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32,
9266+
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
9267+
SDLoc(N0), MVT::i32),
9268+
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
9269+
SDLoc(N0), MVT::i32));
92599270
} else if (Opcode == ISD::XOR) {
92609271
CCMask = Op0CCMaskVal ^ Op1CCMaskVal;
92619272
CCValid = Op0CCValidVal;
92629273
CCReg = Op0CCReg;
9263-
TrueVal = DAG.getNode(ISD::XOR, SDLoc(N0), MVT::i32,
9274+
TrueVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32,
92649275
DAG.getTargetConstant(Op0TrueVal->getZExtValue(),
92659276
SDLoc(N0), MVT::i32),
92669277
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
92679278
SDLoc(N0), MVT::i32));
9268-
FalseVal = N0->getOperand(1);
9279+
FalseVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32,
9280+
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
9281+
SDLoc(N0), MVT::i32),
9282+
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
9283+
SDLoc(N0), MVT::i32));
92699284
} else
92709285
return SDValue();
92719286
} else if (N0->getOpcode() == SystemZISD::SELECT_CCMASK) {
@@ -9326,12 +9341,12 @@ SystemZTargetLowering::combineLogicalOpCCMask(SDNode *N,
93269341
FalseVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32, Op1,
93279342
DAG.getTargetConstant(Op0FalseVal->getZExtValue(),
93289343
SDLoc(N0), MVT::i32));
9329-
} else if (isOneBitSet(Mask ^ 0xf)) {
9344+
} else if (isOneBitSet(Mask ^ Op0CCValidVal)) {
93309345
// Only one clear bit.
93319346
// select_ccmask (Opcode (SRL IPM CC) (Op0TrueVal))
93329347
// (Opcode (CCVal Op0FalseVal)) CCValid/CCMask cc-value must have
93339348
// in FalseVal.
9334-
int CCVal = log2CCMaskToCCVal(Mask ^ 0xf);
9349+
int CCVal = log2CCMaskToCCVal(Mask ^ Op0CCValidVal);
93359350
TrueVal = DAG.getNode(Opcode, SDLoc(N0), MVT::i32, Op1,
93369351
DAG.getTargetConstant(Op0TrueVal->getZExtValue(),
93379352
SDLoc(N0), MVT::i32));

0 commit comments

Comments
 (0)