clang format

Author: lakshayk-nv

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

@@ -180,14 +180,14 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
   // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants
   // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s()
   case llvm::AArch64::OPERAND_MSL_SHIFT: {
-      // There are two valid encodings:
-      //   - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8
-      //   - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16
-      //     Corresponds AArch64_AM::encodeAdvSIMDModImmType7()
-      // But, v2s_msl and v4s_msl instructions accept either form, 
-      // Thus, Arbitrarily chosing 264 (msl #8) for simplicity.
-      AssignedValue = MCOperand::createImm(264);
-      return Error::success();
+    // There are two valid encodings:
+    //   - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8
+    //   - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16
+    //     Corresponds AArch64_AM::encodeAdvSIMDModImmType7()
+    // But, v2s_msl and v4s_msl instructions accept either form,
+    // Thus, Arbitrarily chosing 264 (msl #8) for simplicity.
+    AssignedValue = MCOperand::createImm(264);
+    return Error::success();
   }
   case MCOI::OperandType::OPERAND_PCREL:
   case MCOI::OperandType::OPERAND_FIRST_TARGET: