@@ -11639,37 +11639,17 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
1163911639 (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG ||
1164011640 LHS.getOpcode() == ISD::SIGN_EXTEND)) {
1164111641
11642- SDValue OriginalVal = LHS.getOperand(0);
11643- EVT OriginalVT = LHS.getOpcode() == ISD::SIGN_EXTEND_INREG
11644- ? cast<VTSDNode>(LHS.getOperand(1))->getVT()
11645- : OriginalVal.getValueType();
11646-
11647- // Apply TST optimization for integer types
11648- if (OriginalVT.isInteger()) {
11649- // Calculate the sign bit for the original type
11650- unsigned BitWidth = OriginalVT.getSizeInBits();
11651- APInt SignBit = APInt::getSignedMinValue(BitWidth);
11652- EVT TestVT = (BitWidth <= 32) ? MVT::i32 : MVT::i64;
11653- unsigned TestBitWidth = TestVT.getSizeInBits();
11654- if (BitWidth < TestBitWidth) {
11655- SignBit = SignBit.zext(TestBitWidth);
11656- }
11657-
11658- SDValue SignBitConst = DAG.getConstant(SignBit, DL, TestVT);
11659- SDValue TestOperand = OriginalVal;
11660- if (OriginalVal.getValueType() != TestVT) {
11661- TestOperand = DAG.getNode(ISD::ZERO_EXTEND, DL, TestVT, OriginalVal);
11662- }
11663-
11664- SDValue TST =
11665- DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(TestVT, MVT::i32),
11666- TestOperand, SignBitConst);
11667-
11668- SDValue Flags = TST.getValue(1);
11669- return DAG.getNode(AArch64ISD::CSEL, DL, TVal.getValueType(), TVal,
11670- FVal, DAG.getConstant(AArch64CC::NE, DL, MVT::i32),
11671- Flags);
11672- }
11642+ uint64_t SignBitPos;
11643+ std::tie(LHS, SignBitPos) = lookThroughSignExtension(LHS);
11644+ EVT TestVT = LHS.getValueType();
11645+ SDValue SignBitConst = DAG.getConstant(1ULL << SignBitPos, DL, TestVT);
11646+ SDValue TST =
11647+ DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(TestVT, MVT::i32),
11648+ LHS, SignBitConst);
11649+
11650+ SDValue Flags = TST.getValue(1);
11651+ return DAG.getNode(AArch64ISD::CSEL, DL, TVal.getValueType(), TVal, FVal,
11652+ DAG.getConstant(AArch64CC::NE, DL, MVT::i32), Flags);
1167311653 }
1167411654
1167511655 // Canonicalise absolute difference patterns:
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