@@ -11639,37 +11639,17 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
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(LHS.getOpcode() == ISD::SIGN_EXTEND_INREG ||
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LHS.getOpcode() == ISD::SIGN_EXTEND)) {
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- SDValue OriginalVal = LHS.getOperand(0);
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- EVT OriginalVT = LHS.getOpcode() == ISD::SIGN_EXTEND_INREG
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- ? cast<VTSDNode>(LHS.getOperand(1))->getVT()
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- : OriginalVal.getValueType();
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-
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- // Apply TST optimization for integer types
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- if (OriginalVT.isInteger()) {
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- // Calculate the sign bit for the original type
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- unsigned BitWidth = OriginalVT.getSizeInBits();
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- APInt SignBit = APInt::getSignedMinValue(BitWidth);
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- EVT TestVT = (BitWidth <= 32) ? MVT::i32 : MVT::i64;
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- unsigned TestBitWidth = TestVT.getSizeInBits();
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- if (BitWidth < TestBitWidth) {
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- SignBit = SignBit.zext(TestBitWidth);
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- }
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-
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- SDValue SignBitConst = DAG.getConstant(SignBit, DL, TestVT);
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- SDValue TestOperand = OriginalVal;
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- if (OriginalVal.getValueType() != TestVT) {
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- TestOperand = DAG.getNode(ISD::ZERO_EXTEND, DL, TestVT, OriginalVal);
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- }
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-
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- SDValue TST =
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- DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(TestVT, MVT::i32),
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- TestOperand, SignBitConst);
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-
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- SDValue Flags = TST.getValue(1);
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- return DAG.getNode(AArch64ISD::CSEL, DL, TVal.getValueType(), TVal,
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- FVal, DAG.getConstant(AArch64CC::NE, DL, MVT::i32),
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- Flags);
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- }
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+ uint64_t SignBitPos;
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+ std::tie(LHS, SignBitPos) = lookThroughSignExtension(LHS);
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+ EVT TestVT = LHS.getValueType();
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+ SDValue SignBitConst = DAG.getConstant(1ULL << SignBitPos, DL, TestVT);
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+ SDValue TST =
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+ DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(TestVT, MVT::i32),
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+ LHS, SignBitConst);
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+
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+ SDValue Flags = TST.getValue(1);
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+ return DAG.getNode(AArch64ISD::CSEL, DL, TVal.getValueType(), TVal, FVal,
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+ DAG.getConstant(AArch64CC::NE, DL, MVT::i32), Flags);
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}
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// Canonicalise absolute difference patterns:
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