In MachineScheduler instead of Subtarget.

Author: JonPsson1

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -241,12 +241,6 @@ class MachineSchedStrategy {
   /// Tell the strategy that MBB is about to be processed.
   virtual void enterMBB(MachineBasicBlock *MBB) {};
 
-  virtual bool disableForRegionPreRA(MachineBasicBlock::iterator begin,
-                                     MachineBasicBlock::iterator end,
-                                     unsigned regioninstrs) const {
-    return false;
-  }
-
   /// Tell the strategy that current MBB is done.
   virtual void leaveMBB() {};
 
@@ -496,9 +490,7 @@ class ScheduleDAGMILive : public ScheduleDAGMI {
   bool disableForRegion(MachineBasicBlock *bb,
                         MachineBasicBlock::iterator begin,
                         MachineBasicBlock::iterator end,
-                        unsigned regioninstrs) const override {
-    return SchedImpl->disableForRegionPreRA(begin, end, regioninstrs);
-  }
+                        unsigned regioninstrs) const override;
 
   /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
   /// reorderable instructions.
@@ -1232,10 +1224,6 @@ class GenericScheduler : public GenericSchedulerBase {
 
   void dumpPolicy() const override;
 
-  bool disableForRegionPreRA(MachineBasicBlock::iterator Begin,
-                             MachineBasicBlock::iterator End,
-                             unsigned NumRegionInstrs) const override;
-
   bool shouldTrackPressure() const override {
     return RegionPolicy.ShouldTrackPressure;
   }

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

@@ -16,7 +16,6 @@
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MacroFusion.h"
 #include "llvm/CodeGen/PBQPRAConstraint.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
@@ -230,15 +229,6 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
   virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
                                    unsigned NumRegionInstrs) const {}
 
-  /// Allow the subtarget to leave a region untouched. This has purposefully
-  /// been left a bit untangled from other methods as this is hopefully
-  /// just a temporary solution.
-  virtual bool disableForRegionPreRA(MachineBasicBlock::iterator Begin,
-                                     MachineBasicBlock::iterator End,
-                                     unsigned NumRegionInstrs) const {
-    return false;
-  }
-
   // Perform target-specific adjustments to the latency of a schedule
   // dependency.
   // If a pair of operands is associated with the schedule dependency, DefOpIdx

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -1253,6 +1253,23 @@ void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
          "ShouldTrackLaneMasks requires ShouldTrackPressure");
 }
 
+// EXPERIMENTAL: It seems that GenericScheduler currently often increases
+// spilling heavily with huge regions (like >350 instructions). This option
+// makes any sched region bigger than its value have pre-ra scheduling
+// skipped.
+cl::opt<unsigned> NoSchedAbove("nosched-above", cl::init(~0U));
+bool ScheduleDAGMILive::disableForRegion(MachineBasicBlock *bb,
+                                         MachineBasicBlock::iterator begin,
+                                         MachineBasicBlock::iterator end,
+                                         unsigned regioninstrs) const {
+  if (NumRegionInstrs > NoSchedAbove) {
+    LLVM_DEBUG(dbgs() << "Disabling pre-ra mischeduling of region with "
+               << NumRegionInstrs << " instructions\n";);
+    return true;
+  }
+  return false;
+}
+
 // Setup the register pressure trackers for the top scheduled and bottom
 // scheduled regions.
 void ScheduleDAGMILive::initRegPressure() {
@@ -3335,13 +3352,6 @@ void GenericScheduler::dumpPolicy() const {
 #endif
 }
 
-bool GenericScheduler::disableForRegionPreRA(MachineBasicBlock::iterator Begin,
-                                             MachineBasicBlock::iterator End,
-                                             unsigned NumRegionInstrs) const {
-  const MachineFunction &MF = *Begin->getMF();
-  return MF.getSubtarget().disableForRegionPreRA(Begin, End, NumRegionInstrs);
-}
-
 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
 /// critical path by more cycles than it takes to drain the instruction buffer.
 /// We estimate an upper bounds on in-flight instructions as:

llvm/lib/Target/SystemZ/SystemZSubtarget.cpp

@@ -72,22 +72,6 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
       InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
       TLInfo(TM, *this), FrameLowering(SystemZFrameLowering::create(*this)) {}
 
-
-// EXPERIMENTAL
-cl::opt<unsigned> NoSchedAbove("nosched-above", cl::init(~0U));
-bool SystemZSubtarget::disableForRegionPreRA(MachineBasicBlock::iterator Begin,
-                                             MachineBasicBlock::iterator End,
-                                             unsigned NumRegionInstrs) const {
-  // It seems that the generic scheduler currently can increase spilling heavily
-  // with big / huge regions. Disable it until it is fixed.
-  if (NumRegionInstrs > NoSchedAbove) {
-    LLVM_DEBUG(dbgs() << "Disabling pre-ra mischeduling of region with "
-                      << NumRegionInstrs << " instructions\n";);
-    return true;
-  }
-  return false;
-}
-
 bool SystemZSubtarget::enableSubRegLiveness() const {
   return UseSubRegLiveness;
 }

llvm/lib/Target/SystemZ/SystemZSubtarget.h

@@ -89,12 +89,6 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
   // "source" order scheduler.
   bool enableMachineScheduler() const override { return true; }
 
-  // Don't use pre-ra mischeduler for huge regions where it creates a lot of
-  // spilling (temporary solution).
-  bool disableForRegionPreRA(MachineBasicBlock::iterator Begin,
-                             MachineBasicBlock::iterator End,
-                             unsigned NumRegionInstrs) const override;
-
   // This is important for reducing register pressure in vector code.
   bool useAA() const override { return true; }